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PI7C21P100 2-port pci-x bridge revision 1.06 3545 north first street san jose, ca 95134 ph: 1-877-pericom (1-877-737-4266) fax: 1-408-435-1100 email: solutions@pericom.com internet: http://w ww.pericom.com
life support policy pericom semiconductor corporation?s products are not authorized for use as critical components in life support devices or systems unless a specific written agre ement pertaining to such intended use is executed between the manufacturer and an officer of psc. 1) life support devices or system are devices or systems which: a) are intended for surgical implant into the body or b) support or sustain life and whose failure to pe rform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2) a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. pericom semiconductor corporation re serves the right to make changes to its products or specifications at any time, without notice, in orde r to improve design or performance and to supply the best possible product. pericom semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a pericom semiconductor product. the company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent, patent rights or other rights, of pericom semiconductor corporation. all other trademarks are of their respective companies.
PI7C21P100 2-port pci-x bridge advance information page 3 of 77 june 10, 2005 revision 1.06 revision history date revision number description 12/04/03 1.00 first release of data sheet 12/11/03 1.01 minor text corrections made. 01/22/04 1.02 addition of features section as well as a couple of tables. text corrections. 02/02/04 1.03 corrected device id register bits 11:0 descriptions. 03/15/04 1.04 corrected pin designation for p_rst to e22 in section 3.2.1 09/13/04 1.05 corrected cin max in section 10.2 (dc specifications) from 0.8pf to 8pf added power consumption data in section 10.4 04/13/05 1.051 corrected pin description for test_ce0 (y23) in section 3.2.8 06/10/05 1.06 correct package outline drawing in section 11 added pb-free & green ordering information in section 12
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PI7C21P100 2-port pci-x bridge advance information page 5 of 77 june 10, 2005 revision 1.06 table of contents 1 description.................................................................................................................... ............... 9 2 features ....................................................................................................................... .................. 9 3 signal definitions............................................................................................................. ..... 10 3.1 signal types ....................................................................................................................... 10 3.2 signals ........................................................................................................................ .......... 10 3.2.1 primary bus interface signals............................................................................... 10 3.2.2 primary bus interface signal s ? 64-bit ex tension.......................................... 12 3.2.3 secondary bus int erface signals......................................................................... 13 3.2.4 secondary bus interface sign als ? 64-bit extension.................................... 14 3.2.5 clock sign als................................................................................................................. 1 5 3.2.6 strapping pins and miscellaneous signals ...................................................... 16 3.2.7 jtag boundary scan and test signals ................................................................. 17 3.2.8 test signals................................................................................................................... .. 18 3.2.9 power and ground signals...................................................................................... 18 3.3 pin list ........................................................................................................................... ........ 19 4 pci bus operation.............................................................................................................. ...... 22 4.1 types of transactions.................................................................................................. 22 4.2 write transactions ....................................................................................................... 23 4.2.1 memory write transactions .................................................................................... 23 4.2.1.1 pci-x to pci-x ................................................................................................................. ...... 24 4.2.1.2 pci to pci..................................................................................................................... ........... 24 4.2.1.3 pci to pci-x................................................................................................................... ......... 24 4.2.1.4 pci-x to pci................................................................................................................... ......... 25 4.2.2 delayed/split write transactions........................................................................ 25 4.2.3 immediate write transactions ............................................................................... 25 4.3 read transactions ......................................................................................................... 25 4.3.1 memory read transactions...................................................................................... 26 4.3.1.1 pci-x to pci-x ................................................................................................................. ...... 26 4.3.1.2 pci to pci..................................................................................................................... ........... 26 4.3.1.3 pci to pci-x................................................................................................................... ......... 26 4.3.1.4 pci-x to pci................................................................................................................... ......... 27 4.3.2 i/o read....................................................................................................................... ....... 27 4.3.3 configuration read ................................................................................................... 27 4.3.3.1 type 1 configur ation read ......................................................................................... 27 4.3.3.2 type 0 configur ation read ......................................................................................... 27 4.3.4 non-prefetchable and dword reads.................................................................. 28 4.3.5 prefetchable reads.................................................................................................... 28 4.3.5.1 pci-x to pci-x and pci-x to pci .................................................................................... 28 4.3.5.2 pci to pci..................................................................................................................... ........... 28 4.3.5.3 pci to pci-x................................................................................................................... ......... 29 4.3.6 dynamic prefetch (conventi onal pci mode only) ........................................ 29 4.4 configuration transactions ................................................................................... 29 4.4.1 type 0 access to PI7C21P100....................................................................................... 30 4.4.2 type 1 to type 0 conversion ..................................................................................... 30 4.4.3 type 1 to type 1 forwarding.................................................................................... 31 4.4.4 special cycles ............................................................................................................... 32 5 transaction ordering ........................................................................................................ 32 5.1 general ordering guidelines................................................................................... 33 5.2 ordering rules................................................................................................................. 33 6 clocks......................................................................................................................... ................... 34
PI7C21P100 2-port pci-x bridge advance information page 6 of 77 june 10, 2005 revision 1.06 6.1 primary and secondary clock inputs ................................................................. 34 6.2 clock jitter........................................................................................................................ 3 4 6.3 mode and clock frequency determination ..................................................... 34 6.3.1 primary bus .................................................................................................................... .34 6.3.2 secondary bus ............................................................................................................... 35 6.3.3 clock stab ility.............................................................................................................. 36 6.3.4 driver impedance selection................................................................................... 36 7 reset .......................................................................................................................... ..................... 36 7.1 primary interface reset ............................................................................................. 37 7.2 secondary interface reset ....................................................................................... 37 7.3 bus parking & bus width determination............................................................. 38 7.4 secondary device masking........................................................................................ 38 7.5 address parity errors ................................................................................................. 39 7.6 optional base address register ............................................................................. 39 7.7 optional configuration access from the secondary bus........................ 39 7.8 short term caching ....................................................................................................... 40 8 configuration registers .................................................................................................. 41 8.1 configuration register space map........................................................................ 41 8.1.1.1 signal type de finiti on................................................................................................... 42 8.1.2 vendor id register ? offset 00h............................................................................. 42 8.1.3 device id register ? offset 00h .............................................................................. 42 8.1.4 command register ? offset 04h.............................................................................. 42 8.1.5 primary status register ? offset 04h .................................................................. 43 8.1.6 revision id regist er ? offset 08h ........................................................................... 44 8.1.7 class code regist er ? offset 08h........................................................................... 44 8.1.8 cache line size regi ster ? offset 0ch ................................................................. 44 8.1.9 primary latency timer ? offset 0ch ..................................................................... 44 8.1.10 header type register ? offset 0ch................................................................... 44 8.1.11 bist register ? offset 0ch .................................................................................... 44 8.1.12 lower memory base addres s register ? offset 10h .................................. 45 8.1.13 upper memory base addres s register ? of fset 14h................................... 45 8.1.14 primary bus number register ? offset 18h ................................................... 45 8.1.15 secondary bus number reg ister ? offset 18h ............................................. 45 8.1.16 subordinate bus number register ? offset 18h ......................................... 45 8.1.17 secondary latency timer re gister ? offset 18h ........................................ 45 8.1.18 i/o base address register ? offset 1ch........................................................... 46 8.1.19 i/o limit register ? offset 1ch............................................................................ 46 8.1.20 secondary status regist er ? offset 1ch ....................................................... 46 8.1.21 memory base register ? offset 20h .................................................................. 47 8.1.22 memory limit register ? offset 20h ................................................................. 47 8.1.23 prefetchable memory base re gister ? offs et 24h.................................... 47 8.1.24 prefetchable memory limit re gister ? offs et 24h................................... 47 8.1.25 prefetchable base upper 32-bit register ? offset 28h............................ 47 8.1.26 prefetchable limit upper 32-bit register ? offset 2ch.......................... 48 8.1.27 i/o base upper 16-bit register ? offset 30h.................................................... 48 8.1.28 i/o limit upper 16-bit re gister ? offset 30h .................................................. 48 8.1.29 capability pointer ? offset 34h ......................................................................... 48 8.1.30 expansion rom base address reg ister ? offset 38h .................................. 48 8.1.31 interrupt line register ? offset 3ch.............................................................. 48 8.1.32 interrupt pin register ? offset 3ch ................................................................ 48 8.1.33 bridge control register ? offset 3ch ........................................................... 49 8.1.34 primary data buffering contro l register ? of fset 40h........................ 50 8.1.35 secondary data buffering control register ? offset 40h.................. 51
PI7C21P100 2-port pci-x bridge advance information page 7 of 77 june 10, 2005 revision 1.06 8.1.36 miscellaneous control register ? offset 44h........................................... 52 8.1.37 extended chip control register 1 ? offset 48h......................................... 52 8.1.38 extended chip control register 2 ? offset 48h......................................... 53 8.1.39 arbiter mode register ? offset 50h................................................................. 53 8.1.40 arbiter enable register ? offset 54h.............................................................. 54 8.1.41 arbiter priority regist er ? offset 58h ........................................................... 54 8.1.42 serr# disable register ? offset 5ch ................................................................ 55 8.1.43 primary retry counter register ? offset 60h............................................. 56 8.1.44 secondary retry counter re gister ? offset 64h....................................... 56 8.1.45 discard timer control reg ister ? offset 68h............................................. 57 8.1.46 retry and timer status reg ister ? offset 6ch ............................................ 57 8.1.47 opaque memory enable re gister ? offset 70h ............................................ 57 8.1.48 opaque memory base reg ister ? offset 74h ................................................. 58 8.1.49 opaque memory limit reg ister ? offset 74h ................................................ 58 8.1.50 opaque memory base upper 32-bi t register ? offset 78h ....................... 58 8.1.51 opaque memory limit upper 32-bit register ? offset 7ch...................... 58 8.1.52 pci-x capability id regi ster ? offset 80h ....................................................... 58 8.1.53 next capability pointer register ? offset 80h ........................................... 59 8.1.54 pci-x secondary status re gister ? offset 80h............................................. 59 8.1.55 pci-x bridge primary status register ? offset 84h ................................... 59 8.1.56 secondary bus upstream split transaction register ? offset 88h ... 61 8.1.57 primary bus downstream split transaction register ? offset 8ch .. 61 8.1.58 power management id reg ister ? offset 90h............................................... 61 8.1.59 next capabilities pointer register ? offset 90h........................................ 62 8.1.60 power management capabilities register ? offset 90h.......................... 62 8.1.61 power management control and status register ? offset 94h ......... 62 8.1.62 pci-to-pci bridge support extension register ? offset 94h ................. 63 8.1.63 secondary bus private device mask register ? offset b0h................... 63 8.1.64 miscellaneous control register 2 ? offset b8h ....................................... 64 9 ieee 1149.1 compatible jtag cont roller .................................................................. 65 9.1 instruction register..................................................................................................... 65 9.2 bypass register ................................................................................................................ 65 9.3 device id register ........................................................................................................... 65 9.4 boundary scan register ............................................................................................. 66 9.5 jtag boundary register order................................................................................ 66 10 electrical info rmation.................................................................................................... 74 10.1 maximum ratings ............................................................................................................ 74 10.2 dc specifications............................................................................................................. 74 10.3 ac specifications............................................................................................................. 74 10.4 power consumption ....................................................................................................... 75 11 mechanical information.................................................................................................. 76 12 ordering information........................................................................................................ 76
PI7C21P100 2-port pci-x bridge advance information page 8 of 77 june 10, 2005 revision 1.06 list of tables t able 3-1 pin list 304-pin pbga........................................................................................................... 19 t able 4-1 pci and pci-x transactions .......................................................................................... 22 t able 4-2 write transaction forwarding ............................................................................... 23 t able 4-3 read transactin handling.......................................................................................... 25 t able 4-4 device number to idsel.................................................................................................. 31 t able 5-1 summary of transaction ordering in pci mode ............................................... 33 t able 5-2 summary of transaction ordering in pci-x mode ........................................... 33 t able 6-1 programmable pull-up circuit................................................................................. 35 t able 6-2 driver impedance selection ....................................................................................... 36 t able 7-1 delay times for de-assertion of s_rst# ................................................................ 38 t able 7-2 de-assertion of s_rst#.................................................................................................... 38 t able 8-1 configuration space map ............................................................................................. 41 t able 9-1 jtag boundary scan register .................................................................................... 66 t able 10-1 ac timing specifications pci-x mode...................................................................... 75 t able 10-2 ac timing specifications conventional pci mode.......................................... 75 list of figures f igure 10-1 pci signal timing measurements ........................................................................... 74 f igure 11-1 package diagram 31 x 31 mm 304-pin hpbga ........................................................... 76
PI7C21P100 2-port pci-x bridge advance information page 9 of 77 june 10, 2005 revision 1.06 1 description the PI7C21P100 is a 2-port pci-x 2.0 bridge designed to be compliant with the pci-x addendum to the local bus specification revision 1.0a. the PI7C21P100 is able to handle 64-bit data at a maximum bus frequency of 133mhz. the PI7C21P100 is designed for high speed applications such as ethernet, scsi, and fibre channel. the PI7C21P100 may also be used for bus expansion, frequency isolations/translations, or pci-x to pci isolations/translations. 2 features - industry standards compliance ? pci-x addendum to the local bus specification revision 1.0a (mode 1 only) ? pci local bus specification revision 2.2 ? pci-to-pci bridge architecture specification revision 1.1 ? pci power management interface specification revision 1.1 ? supports d0 and d3 power states - interface ? 3.3v signaling with 5v tolerance ? 133mhz / 64-bit operation on both buses ? dual address cycle support ? concurrent primary and secondary bus operation ? primary and secondary may be run in either pci mode or pci-x mode 1 ? asynchronous operation support ? programmable internal arbiter with suppor t for up to 6 external masters on the secondary bus ? internal arbiter may be disabled to use an external arbiter ? ieee 1149.1 jtag support - operation ? type 0 and type 1 configuration support ? configuration register access from both primary and secondary buses ? 2kb of buffering for upstream memory burst read commands ? 2kb of buffering for downstream memory burst read commands ? 1kb of buffering for upstream posted memory write commands ? 1kb of buffering for downstream posted memory write commands ? support for up to 8 active transactions in each direction - additional features ? capabilities pointer ? ability to define an opaque memory address ? definable base address register ? secondary side pci-x device privatization - packaging ? 304-pin pbga, 31 x 31 mm
PI7C21P100 2-port pci-x bridge advance information page 10 of 77 june 10, 2005 revision 1.06 3 signal definitions 3.1 signal types signal type description i input only o output only p power ts tri-state bi-directional sts sustained tri-state. active low signal must be pulled high for 1 cycle when deasserting. od open drain iu internal pull-up on signal id internal pull-down on signal 3.2 signals signal names that end with ?#? are active low. 3.2.1 primary bus interface signals name pin # type description p_ad[31:0] j23, m21, m22, l21, l22, g23, k20, e23, k21, d23, k22, j21, j22, h21, h22, g21, b20, g22, f20, f22, d18, c19, c17, b17, a20, c16, b16, a19, c15, b14, c13, b13 ts primary address / data: multiplexed address and data bus. address is indicated by p_frame# assertion. write data is stable and valid when p_irdy# is asserted and read data is stable and valid when p_trdy# is asserted. data is transferre d on rising clock edges when both p_irdy# and p_trdy# are asserted. during bus idle, PI7C21P100 drives p_ad[31:0] to a valid logic level when p_gnt# is asserted. p_cbe[3:0]# a15, d14, b18, a13 ts primary command/byte enables: multiplexed command field and byte enable field. during address phase, the initiator drives th e transaction type on these pins. after that, the initiato r drives the byte enables during data phases. during bus idle, PI7C21P100 drives p_cbe[3:0]# to a valid l ogic level when p_gnt# is asserted. p_par c18 ts primary parity. p_par is even parity of p_ad[31:0] and p_cbe[3:0] (i.e. an even number of 1?s). p_par is valid and stable one cycle after the address phase (indicated by assertion of p_frame#) for address parity. for write data phase s, p_par is valid one clock after p_irdy# is asserted. for read data phase, p_par is valid one clock after p_trdy# is asserted. signal p_par is tri-stated one cycle after the p_ad lines are tri-stated. during bus idle, PI7C21P100 drives p_par to a valid logic level wh en p_gnt# is asserted. p_frame# a17 sts primary frame (active low). driven by the initiator of a transaction to indicate the beginning and duration of an access. the de-assertion of p_frame# indicates the final data phase requested by the initiator. before being tri-stated, it is driven high for one cycle. p_irdy# a16 sts primary irdy (active low). driven by the initiator of a transaction to indicate its ability to complete current data phase on the primary side . once asserted in a data phase, it is not de-asserted until the end of the data phase. before tri-stated, it is driven high for one cycle.
PI7C21P100 2-port pci-x bridge advance information page 11 of 77 june 10, 2005 revision 1.06 name pin # type description p_trdy# b15 sts primary trdy (active low). driven by the target of a transaction to indicate its ability to complete current data phase on the primary side . once asserted in a data phase, it is not de-asserted until the end of the data phase. before tri-stated, it is driven high for one cycle. p_devsel# d21 sts primary device select (active low). asserted by the target indicating that the device is accepting the transaction. as a master, PI7C21P100 waits for the assertion of this signal with in 5 cycles of p_frame# assertion; otherwise, terminat e with master abort. before tri-stated, it is driven high for one cycle. p_stop# c4 sts primary stop (active low). asserted by the target indicating that the target is requesting the initiator to stop the current transaction. befo re tri-stated, it is driven high for one cycle. p_lock# c14 i primary lock (active low). asserted by an initiator, one clock cycle after the first address phase of a transaction, attempting to perform an operation that may take more than one pci transaction to complete. p_idsel b19 i primary id select. used as a chip select line for type 0 configuration access to pi721p100 configuration space. p_perr# c8 sts primary parity error (active low). asserted when a data parity error is detected for data received on the primary interface. before being tri-stated, it is driven high for one cycle. p_serr# b4 od primary system error (active low). can be driven low by any device to indicate a system error condition. PI7C21P100 drives this pin on: ? address parity error ? posted write data par ity error on target bus ? secondary s_serr# asserted ? master abort during posted write transaction ? target abort during posted write transaction ? posted write transaction discarded ? delayed write request discarded ? delayed read request discarded ? delayed transaction master timeout this signal requires an external pull-up resistor for proper operation. p_req# b21 ts primary request (active low): this is asserted by PI7C21P100 to indicate that it wants to start a transaction on the primary bus. PI7C21P100 de-asserts this pin for at least 2 pci clock cycles before asserting it again. p_gnt# c20 i primary grant (active low): when asserted, PI7C21P100 can access the primary bus. during idle and p_gnt# asserted, PI7C21P100 will drive p_ad, p_cbe, and p_par to valid logic levels. p_rst# e22 i primary reset (active low): when p_reset# is active, all pci signals should be asynchronously tri- stated.
PI7C21P100 2-port pci-x bridge advance information page 12 of 77 june 10, 2005 revision 1.06 3.2.2 primary bus interface signals ? 64-bit extension name pin # type description p_ad[63:32] b11, d10, c10, a4, b10, c9, b9, a3, b8, b3, c7, b7, d6, b6, b5, c2, d2, f4, e3, f3, b1, f2, g3, h3, h2, e1, j3, g1, h1, j2, j1, l1 ts primary upper 32-bit address / data: multiplexed address and data bus providing an additional 32 bits to the primary. when a dual address command is used and p_req64# is asserted, the initiator drives the upper 32 bits of the 64-bit address. otherwise, these bits are undefined and driven to valid logic levels. during the data phase of a transaction, the initiator drives the upper 32 bits of the 64-bit write data , or the target drives the upper 32 bits of the 64-bit read data, when p_req64# and p_ack64# are both asserted. otherwise, these bits are pulled up to a valid logic level through external resistors. p_cbe[7:4]# a7, b12, c11, a5 ts primary upper 32-bit command/byte enables: multiplexed command field and byte enable field. during address phase, when the dual address command is used and p_req64# is asse rted, the initiator drives the transaction type on these pins. otherwise, these bits are undefined, and the initiator drives a valid logic level onto the pins. for read and write transactions, the initiator drives these bits for the p_ad[63:32] data bits when p_req64# and p_ack64# are both asserted. when not driven, these bits are pulled up to a valid logic level through external resistors. p_par64 a9 ts primary upper 32-bit parity: p_par64 carries the even parity of p_ad[63:32] and p_cbe[7:4] for both address and data phases. p_par64 is driven by the initiator and is valid 1 cycle after the first address phase when a dual address command is used and p_req64# is asserted. p_par64 is valid 1 clock cycle after the second address phase of a dual address transaction when p_req64# is asserted. p_par64 is valid 1 cycle after valid data is driven when both p_req64# and p_ack64# are asserted for that data phase. p_par64 is driven by the device driving read or write data 1 cycle after the p_ad lines are driven . p_par64 is tri-stated 1 cycle after the p_ad lines are tri-stated. devices receive data sample p_par64 as an input to check for possible parity errors during 64-bit transactions. when not driven, p_par64 is pulled up to a valid logic level through external resistors. p_req64# c12 sts primary 64-bit transfer request: p_req64# is asserted by the initiator to indicate that the initiator is requesting a 64-bit data transfer. p_req64# has the same timing as p_frame#. when p_req64# is asserted low during reset, a 64-bit data path is supported. when p_req64# is high during reset, PI7C21P100 drives p_ad[63:32], p_cbe[7:4], and p_par64 to valid logic levels. when deasserting, p_req64# is driven high for 1 cycle and then sustained by an external pull-up resistor. p_ack64# a2 sts primary 64-bit transfer acknowledge: p_ack64# is asserted by the target only when p_req64# is asserted by the initiator to indicate the target?s ability to transfer data using 64 bits. p_ack64# has the same timing as p_devsel#. when deasserting, p_ack64# is driven high for 1 cycle and then is sustained by an external pull-up resistor.
PI7C21P100 2-port pci-x bridge advance information page 13 of 77 june 10, 2005 revision 1.06 3.2.3 secondary bus interface signals name pin # type description s_ad[31:0] n22, n21, p22, p21, m23, p20, n23, r22, t23, r21, w23, t22, u22, u21, v22, v21, w21, v20, aa20, ab18, y18, aa16, ab15, ac17, aa13, aa12, ac15, ab11, ac11, ac9, ab9, aa9 ts secondary address/data: multiplexed address and data bus. address is indicated by s_frame# assertion. write data is stable and valid when s_irdy# is asserted and read data is stable and valid when s_irdy# is asserted. data is transfe rred on rising clock edges when both s_irdy# and s_trdy# are asserted. during bus idle, PI7C21P100 drives s_ad[31:0] to a valid logic level when the bridge is granted the bus. s_cbe[3:0]# aa15, ab14, ab16, ab12 ts secondary command/byte enables: multiplexed command field and byte enable field. during address phase, the initiator drives th e transaction type on these pins. the initiator then driv es the byte enables during data phases. during bus idle, PI7C21P100 drives s_cbe[3:0] to a valid logic level when the bridge is granted the bus. s_par aa17 ts secondary parity: s_par is an even parity of s_ad[31:0] and s_cbe[3:0] (i.e. an even number of 1?s). s_par is valid and stable one cycle after the address phase (indicated by assertion of s_frame#) for address parity. for write data phases, s_par is valid one clock after s_irdy# is asserted. for read data phase, s_par is valid one clock after s_trdy# is asserted. signal s_par is tri-stated one cycle after the s_ad lines are tri-stated. during bus idle, PI7C21P100 drives s_par to a valid logic level when the bridge is granted the bus. s_frame# aa14 sts secondary frame (active low): driven by the initiator of a transaction to indicate the beginning and duration of an access. the de-assertion of s_frame# indicates the final data phase requested by the initiator. before being tri-stated, it is driven high for one cycle. s_irdy# ac19 sts secondary irdy (active low): driven by the initiator of a transaction to indicate its ability to complete current data phase on the secondary side. once asserted in a data phase, it is not de-asserted until the end of the data phase. before tr i-stated, it is driven high for one cycle. s_trdy# y14 sts secondary trdy (active low): driven by the target of a transaction to indicate its ability to complete current data phase on the secondary side. once asserted in a data phase, it is not de-asserted until the end of the data phase. before tri-stated, it is driven high for one cycle. s_devsel# ac21 sts secondary device select (active low): asserted by the target indicating that the device is accepting the transaction. as a master, PI7C21P100 waits for the assertion of this signal with in 5 cycles of s_frame# assertion; otherwise, terminat e with master abort. before tri-stated, it is driven high for one cycle. s_stop# ab20 sts secondary stop (active low): asserted by the target indicating that the targ et is requesting the initiator to stop the current transaction. before tri-stated, it is driven high for one cycle. s_lock# ac20 sts secondary lock (active low): asserted by an initiator, one clock cycle after the first address phase of a transaction, when it is pr opagating a locked transaction downstream. PI7C21P100 does not propagate locked transactions upstream. s_perr# ab17 sts secondary parity e rror (active low): asserted when a data parity error is detected for data received on the secondary interface. before being tri-stated, it is driven high for one cycle.
PI7C21P100 2-port pci-x bridge advance information page 14 of 77 june 10, 2005 revision 1.06 name pin # type description s_serr# ab19 i secondary system error (active low): can be driven low by any device to indicate a system error condition. s_req[6:2]# ac3, ab5, ab3, w2, aa2 i secondary request (active low): this is asserted by an external device to indicate that it wants to start a transaction on the secondary bus. the input is externally pulled up through a resistor to vdd. s_req[1]# aa23 i secondary request (active low): when the internal ar biter is enabled, this is asserted by an external device to indicate that it wants to start a transaction on the secondary bus. the input is externally pulled up through a resistor to vdd. when the internal ar biter is disabled, this is used by PI7C21P100 as its gnt input. s_gnt[6:2]# ac4, ab4, ac5, y2, ab1 ts secondary grant (active low): PI7C21P100 asserts these pins to allow exte rnal masters to access the secondary bus. PI7C21P100 de-asserts these pins for at least 2 pci clock cycles before asserting it again. during idle and s_gnt# deasserted, PI7C21P100 will drive s_ad, s_cbe, and s_par. s_gnt[1]# aa19 ts secondary grant (active low): when the internal arbiter is enabled, PI7C21P100 asserts this pin to allow external masters to access the secondary bus. PI7C21P100 de-asserts this pin for at least 2 pci clock cycles before asserting it again. during idle and s_gnt# deasserted, PI7C21P100 will drive s_ad, s_cbe, and s_par. when the internal ar biter is disabled, this is used by PI7C21P100 as its req output. s_rst# u23 o secondary reset (active low): asserted when any of the following conditions are met: 1. signal p_reset# is asserted. 2. secondary reset bit in bri dge control register in configuration space is set. 3. the chip reset bit in the chip control register in configuration space is set. when asserted, all control signals are tri-stated and zeroes are driven on s_ad, s_cbe, s_par, and s_par64. 3.2.4 secondary bus interface si gnals ? 64-bit extension name pin # type description s_ad[63:32] ab8, ab7, aa7, ab6, aa6, aa5, y6, y3, v2, v4, u2, u3, t2, t3, r2, r3, p2, y1, p3, w1, p4, u1, n2, n3, m2, m3, r1, l2, l3, k2, k3, k4 ts secondary upper 32-bit address/data: multiplexed address and data bus. a ddress is indicated by s_frame# assertion. write data is stable and valid when s_irdy# is asserted a nd read data is stable and valid when s_irdy# is assert ed. data is transferred on rising clock edges when both s_irdy# and s_trdy# are asserted. during bus idle, PI7C21P100 drives s_ad to a valid logic level when th e bridge is granted the bus. s_cbe[7:4]# y10, ab10, aa11, ac8 ts secondary upper 32-bit command/byte enables: multiplexed command field and byte enable field. during address phase, the initia tor drives the transaction type on these pins. the initia tor then drives the byte enables during data phases. during bus idle, PI7C21P100 drives s_cbe[7:0] to a valid logic level when the bridge is granted the bus.
PI7C21P100 2-port pci-x bridge advance information page 15 of 77 june 10, 2005 revision 1.06 name pin # type description s_par64 aa10 ts secondary upper 32-bit parity: s_par64 carries the even parity of s_ad[63:32] and s_cbe[7:4] for both address and data phases. s_par64 is driven by the initiator and is valid 1 cycle after the first address phase when a dual address command is used and s_req64# is asserted. s_par64 is valid 1 clock cycle after the second address phase of a dual address transaction when s_req64# is asserted. s_par64 is valid 1 cycle after valid data is driven when both s_req64# and s_ack64# are asserted for that data phase. s_par64 is driven by the device driving read or write data 1 cycle after the s_ad lines are driven . s_par64 is tri-stated 1 cycle after the s_ad lines are tri-stated. devices receive data sample s_par64 as an input to check for possible parity errors during 64-bit transactions. when not driven, s_par64 is pulled up to a valid logic level through external resistors. s_req64# ab13 sts secondary 64-bit transfer request: s_req64# is asserted by the initiator to indicate that the initiator is requesting a 64-bit data transfer. s_req64# has the same timing as s_frame#. when s_req64# is asserted low during reset, a 64-bit data path is supported. when s_req64# is high during reset, PI7C21P100 drives s_ad[63:32], s_cbe[7:4], and s_par64 to valid logic levels. when deasserting, s_req64# is driven to a deasserted state for 1 cycle and then sustained by an external pull-up resistor. s_ack64# aa8 sts secondary 64-bit transfer acknowledge: s_ack64# is asserted by the target only when s_req64# is asserted by the initiator to i ndicate the target?s ability to transfer data using 64 bits. s_ack64# has the same timing as s_devsel#. when deasserting, s_ack64# is driven to a deasserted st ate for 1 cycle and then is sustained by an external pull-up resistor. 3.2.5 clock signals name pin # type description p_clk e21 i primary clock input: provides timing for all transactions on the primary interface. for conventional pci mode, the input clock fr equency may be between 0 ? 66mhz. in pci-x mode, the input clock frequency may be between 66 ? 133m hz. see section 6 for limitations. s_clk ab23 i secondary clock input: provides timing for all transactions on the secondary interface. for conventional pci mode, the input clock fr equency may be between 0 ? 66mhz. in pci-x mode, the input clock frequency may be between 66 ? 133m hz. see section 6 for limitations. if the primary bus is running at 133mhz, the minimum frequency that may be supplied to s_clk is 33mhz.
PI7C21P100 2-port pci-x bridge advance information page 16 of 77 june 10, 2005 revision 1.06 3.2.6 strapping pins and mi scellaneous signals name pin # type description s__arb# t21 i internal arbiter enable: this pin is used by PI7C21P100 to determine whether the secondary bus uses the internal arbiter or external arbiter. 0: enable the internal arbiter 1: disable the internal arbite r and use an external arbiter s_sel100 v3 i secondary bus maximum frequency: this pin is used to determine the maximum frequency on the secondary bus when in pci-x mode. in pci mode, the pin has no function and should not be left floating. 0: set secondary interface to 133mhz 1: set secondary interface to 100mhz s_pcixcap r23 i secondary bus pci-x capable: this pin is used with s_sel100 to determine the fr equency and mode for the secondary bus. there are three conditions for this pin determining the capability of the secondary bus: ground: not capable of pci-x mode pull-down: pci-x 66mhz not connected: pci-x 133mhz s_pcixcap_pu aa1 i s_pcixcap pull-up driver: this pin is used with s_pcixap as part of a programmable pull-up circuit to determine the state of s_pcixcap. a 1kohm resistor must be placed between this pin and s_pcixcap. s_drvr ac7 id secondary driver mode: this pin controls the output impedance of the secondary drivers to account for the number of loads on the secondary bus. 0: default impedance 1: select alternate impedance see table 6-2 for impedance values. p_drvr e2 id primary driver mode control: controls the output impedance of the primary bus drivers to account for the number of loads on the primary bus. 0: default impedance 1: select alternate impedance s_clk_stable w3 i s_clk input stable: determines when the s_clk is stable to resolve when s_ rst# can by de-asserted. 0: s_clk is not stable 1: s_clk is stable s_idsel aa22 i initialization device select: s_idsel is used as a chip select during configuration reads and writes on the secondary bus. applications that do not require access to PI7C21P100?s configuration registers from the secondary side should pull this pin low.
PI7C21P100 2-port pci-x bridge advance information page 17 of 77 june 10, 2005 revision 1.06 64bit_dev# y22 i pci-x device bus width: 64bit_dev# sets bit 16 of the pci-x bridge status register to support system management software. this signal does not change the behavior of the bridge. 0: sets bit 16 of the pci-x bridge status register to 1 1: sets bit 16 of the pci-x bridge status register to 0 bar_en g2 i base address register enable: bar_en is used to enable the base address at reset or power up. when enabled, the 64-bit register at offset 10h and offset 14h is used to claim a 1mb memory region. 0: disabled ? register retu rns 0 and no memory region is claimed 1: enabled ? bits 63:20 can be written by software to claim a 1mb memory region idsel_route ac22 i idsel reroute enable: controls the idsel reroute function at reset or power up. the reset value of the secondary bus private device mask register is changed according to the value of this pin. 0: reset value of the secondary bus private device mask register is 00000000h 1: reset value of the secondary bus private device mask register is 22f20000h opaque_en aa18 i opaque region enable: used to enable the opaque memory region at reset or power up. controls bit[0] offset 70h. 0: disable opaque memory address range 1: enable opaque memory address range p_cfg_busy c6 i primary configuration busy: determines the value of bit [2] offset 44h to sequence initialization on the primary and secondary buses for applications that require bridge configurati on from the secondary bus. applications that do not requi re configuration from the secondary bus should pull this pin down to ground. 0: type 0 configuration commands accepted normally on the primary bus. 1: type 0 configuration commands are retried on the primary bus. reserved d1 - reserved. must be tied to ground. 3.2.7 jtag boundary scan and test signals name pin # type description tck f21 iu test clock. used to clock state information and data into and out of the pi721p100 during boundary scan. tms d22 iu test mode select. used to control the state of the test access port controller. tdo b23 o test data output. used as the serial output for the test instructions and data from the test logic. tdi c22 iu test data input. serial input for the jtag instructions and test data. trst# c23 iu test reset. active low signal to reset the test access port (tap) controller into an initialized state.
PI7C21P100 2-port pci-x bridge advance information page 18 of 77 june 10, 2005 revision 1.06 3.2.8 test signals name pin # type description t_di1 y21 iu pll bypass control for pci-x mode. the strapped value of this pin (at p_rst# deassertion) controls whether the internal pll?s are bypassed in pci-x mode. high: pll?s are used in pci-x mode low: pll?s are bypassed in pci-x mode t_di2 aa4 iu shorten initialization period. controls the period for the following signals during initialization. low: shorten periods t pirstdly - 5 primary clocks t xcap ? 6 primary clocks t sirstdly - 40 secondary clocks t srstdly ? 11 secondary clocks + 7 primary clocks high: normal initialization t pirstdly ? see table 7-2 t xcap ? see table 7-2 t sirstdly ? see table 7-2 t srstdly ? see table 7-2 t_modectl t_ri xclk_out c1 w22 d3 i i i pll test control. controls along with the internal pll testing. t_ri t_modectl xclk_out h l z h h p_clk* l h s_clk** * p_pll enabled, s_pll disabled **p_pll disabled, s_pll enabled t_ri w22 i pll bypass control for pci mode. the strapped value of this pin (at t_ri) c ontrols whether the internal pll?s are bypassed in pci mode. 1: pll?s are bypassed in pci mode 0 and t_modectl=0: pll?s are used in pci mode test_ce0 y23 id reserved. chip testing only. tie low for normal operation. 3.2.9 power and ground signals name pin # type description p_vdda a21 p 2.5v power: power supply to the pll for the primary clock domain. p_vssa d16 p 2.5v power: ground for the pll for the primary clock domain. s_vdda ab21 p 2.5v power: power supply to the pll for the secondary clock domain. s_vssa y16 p 2.5v power: ground for the pll for the secondary clock domain. vdd d9, d11, d13, d15, j4, j20, l4, l20, n4, n20, r4, r20, y9, y11, y13, y15 p 2.5 power: power supply for the internal logic
PI7C21P100 2-port pci-x bridge advance information page 19 of 77 june 10, 2005 revision 1.06 name pin # type description vdd2 a8, a12, a22, c5, d5, d7, d17, d19, e4, e20, g4, g20, h23, m1, t1, u4, u20, w4, w20, y5, y7, y17, y19, ac2, ac12, ac16 p 3.3 power: power supply for the i/o vss a1, a6, a10, a11, a14, a18, a23, b2, b22, c3, c21, d4, d8, d12, d20, f1, f23, h4, h20, k1, k23, l23, m4, m20, n1, p1, p23, t4, t20, v1, v23, y4, y8, y12, y20, aa3, aa21, ab2, ab22, ac1, ac6, ac10, ac13, ac14, ac18, ac23 p ground 3.3 pin list table 3-1 pin list 304-pin pbga ball location pin name type ball location pin name type a1 vss p a2 p_ack64# sts a3 p_ad[56] ts a4 p_ad[60] ts a5 p_cbe[4]# ts a6 vss p a7 p_cbe[7]# ts a8 vdd2 p a9 p_par64 ts a10 vss p a11 vss p a12 vdd2 p a13 p_cbe[0]# ts a14 vss p a15 p_cbe[3]# ts a16 p_irdy# sts a17 p_frame# sts a18 vss p a19 p_ad[4] ts a20 p_ad[7] ts a21 p_vdda p a22 vdd2 p a23 vss p b1 p_ad[43] ts b2 vss p b3 p_ad[54] ts b4 p_serr# od b5 p_ad[49] ts b6 p_ad[50] ts b7 p_ad[52] ts b8 p_ad[55] ts b9 p_ad[57] ts b10 p_ad[59] ts b11 p_ad[63] ts b12 p_cbe[6]# ts b13 p_ad[0] ts b14 p_ad[2] ts b15 p_trdy# sts b16 p_ad[5] ts b17 p_ad[8] ts b18 p_cbe[1]# ts b19 p_idsel i b20 p_ad[15] ts b21 p_req# ts b22 vss p b23 tdo o c1 t_modectl i c2 p_ad[48] ts c3 vss p c4 p_stop# sts c5 vdd2 p c6 p_cfg_busy i c7 p_ad[53] ts c8 p_perr# sts c9 p_ad[58] ts c10 p_ad[61] ts c11 p_cbe[5]# ts c12 p_req64# sts c13 p_ad[1] ts c14 p_lock# i c15 p_ad[3] ts c16 p_ad[6] ts c17 p_ad[9] ts c18 p_par ts c19 p_ad[10] ts c20 p_gnt# i c21 vss p c22 tdi i c23 trst# i d1 reserved -
PI7C21P100 2-port pci-x bridge advance information page 20 of 77 june 10, 2005 revision 1.06 ball location pin name type ball location pin name type d2 p_ad[47] ts d3 xclk_out i d4 vss p d5 vdd2 p d6 p_ad[51] ts d7 vdd2 p d8 vss p d9 vdd p d10 p_ad[62] ts d11 vdd p d12 vss p d13 vdd p d14 p_cbe[2]# ts d15 vdd p d16 p_vssa p d17 vdd2 p d18 p_ad[11] ts d19 vdd2 p d20 vss p d21 p_devsel# sts d22 tms i d23 p_ad[22] ts e1 p_ad[38] ts e2 p_drver i e3 p_ad[45] ts e4 vdd2 p e20 vdd2 p e21 p_clk i e22 p_rst# i e23 p_ad[24] ts f1 vss p f2 p_ad[42] ts f3 p_ad[44] ts f4 p_ad[46] ts f20 p_ad[13] ts f21 tck i f22 p_ad[12] ts f23 vss p g1 p_ad[36] ts g2 bar_en i g3 p_ad[41] ts g4 vdd2 p g20 vdd2 p g21 p_ad[16] ts g22 p_ad[14] ts g23 p_ad[26] ts h1 p_ad[35] ts h2 p_ad[39] ts h3 p_ad[40] ts h4 vss p h20 vss p h21 p_ad[18] ts h22 p_ad[17] ts h23 vdd2 p j1 p_ad[33] ts j2 p_ad[34] ts j3 p_ad[37] ts j4 vdd p j20 vdd p j21 p_ad[20] ts j22 p_ad[19] ts j23 p_ad[31] ts k1 vss p k2 s_ad[34] ts k3 s_ad[33] ts k4 s_ad[32] ts k20 p_ad[25] ts k21 p_ad[23] ts k22 p_ad[21] ts k223 vss p l1 p_ad[32] ts l2 s_ad[36] ts l3 s_ad[35] ts l4 vdd p l20 vdd p l21 p_ad[28] ts l22 p_ad[27] ts l23 vss p m1 vdd2 p m2 s_ad[39] ts m3 s_ad[38] ts m4 vss p m20 vss p m21 p_ad[30] ts m22 p_ad[29] ts m23 s_ad[27] ts n1 vss p n2 s_ad[41] ts n3 s_ad[40] ts n4 vdd p n20 vdd p n21 s_ad[30] ts n22 s_ad[31] ts n23 s_ad[25] ts p1 vss p p2 s_ad[47] ts p3 s_ad[45] ts p4 s_ad[43] ts p20 s_ad[26] ts p21 s_ad[28] ts p22 s_ad[29] ts p23 vss p r1 s_ad[37] ts r2 s_ad[49] ts r3 s_ad[48] ts r4 vdd p r20 vdd p r21 s_ad[22] ts r22 s_ad[24] ts r23 s_pcixcap i t1 vdd2 p t2 s_ad[51] ts t3 s_ad[50] ts t4 vss p t20 vss p t21 s_arb# i t22 s_ad[20] ts t23 s_ad[23] ts u1 s_ad[42] ts u2 s_ad[53] ts u3 s_ad[52] ts u4 vdd2 p u20 vdd2 p u21 s_ad[18] ts u22 s_ad[19] ts u23 s_rst# o
PI7C21P100 2-port pci-x bridge advance information page 21 of 77 june 10, 2005 revision 1.06 ball location pin name type ball location pin name type v1 vss p v2 s_ad[55] ts v3 s_sel100 i v4 s_ad[54] ts v20 s_ad[14] ts v21 s_ad[16] ts v22 s_ad[17] ts v23 vss p w1 s_ad[44] ts w2 s_req[3]# i w3 s_clk_stable i w4 vdd2 p w20 vdd2 p w21 s_ad[15] ts w22 t_ri i w23 s_ad[21] ts y1 s_ad[46] ts y2 s_gnt[3]# ts y3 s_ad[56] ts y4 vss p y5 vdd2 p y6 s_ad[57] ts y7 vdd2 p y8 vss p y9 vdd p y10 s_cbe[7]# ts y11 vdd p y12 vss p y13 vdd p y14 s_trdy# sts y15 vdd p y16 s_vssa p y17 vdd2 p y18 s_ad[11] ts y19 vdd2 p y20 vss p y21 t_di1 i y22 64bit_dev# i y23 test_ce0 i aa1 s_pcixcap_pu i aa2 s_req[2]# i aa3 vss p aa4 t_di2 i aa5 s_ad[58] ts aa6 s_ad[59] ts aa7 s_ad[61] ts aa8 s_ack64# sts aa9 s_ad[0] ts aa10 s_par64 ts aa11 s_cbe[5]# ts aa12 s_ad[6] ts aa13 s_ad[7] ts aa14 s_frame# sts aa15 s_cbe[3]# ts aa16 s_ad[10] ts aa17 s_par ts aa18 opaque_en i aa19 s_gnt[1]# ts aa20 s_ad[13] ts aa21 vss p aa22 s_idsel i aa23 s_req[1]# i ab1 s_gnt[2]# ts ab2 vss p ab3 s_req[4]# i ab4 s_gnt[5]# ts ab5 s_req[5]# i ab6 s_ad[60] ts ab7 s_ad[62] ts ab8 s_ad[63] ts ab9 s_ad[1] ts ab10 s_cbe[6]# ts ab11 s_ad[4] ts ab12 s_cbe[0]# ts ab13 s_req64# sts ab14 s_cbe[2]# ts ab15 s_ad[9] ts ab16 s_cbe[1]# ts ab17 s_perr# sts ab18 s_ad[12] ts ab19 s_serr# i ab20 s_stop# sts ab21 s_vdda p ab22 vss p ab23 s_clk i ac1 vss p ac2 vdd2 p ac3 s_req[6]# i ac4 s_gnt[6]# ts ac5 s_gnt[4]# ts ac6 vss p ac7 s_drvr i ac8 s_cbe[4]# ts ac9 s_ad[2] ts ac10 vss p ac11 s_ad[3] ts ac12 vdd2 p ac13 vss p ac14 vss p ac15 s_ad[5] ts ac16 vdd2 p ac17 s_ad[8] ts ac18 vss p ac19 s_irdy# sts ac20 s_lock# sts ac21 s_devsel# sts ac22 idsel_route i ac23 vss p
PI7C21P100 2-port pci-x bridge advance information page 22 of 77 june 10, 2005 revision 1.06 4 pci bus operation this chapter offers information about pci transactions, transaction forwarding across PI7C21P100, and transaction termination. the PI7C21P100 has two 2kb buffers for read data buffering of upstream and downstream transactions. also, PI7C21P100 has two 1kb buffers for write data buffering of upstream and downstream transactions. 4.1 types of transactions this section provides a summary of pci and pci-x transactions performed by PI7C21P100. table 4-1 lists the command code and name of each pci and pci-x transaction. the master and target columns indicate support for each transaction when PI7C21P100 initiates transactions as a master, on the primary a nd secondary buses, and when PI7C21P100 responds to transactions as a target, on the primary and secondary buses. table 4-1 pci and pci-x transactions types of transactions initiates as master responds as target primary secondary primary secondary 0000 interrupt acknowledge n n n n 0001 special cycle y y n n 0010 i/o read y y y y 0011 i/o write y y y y 0100 reserved n n n n 0101 reserved n n n n 0110 memory read y y y y 0111 memory write y y y y 1000 reserved n n n n 1001 reserved n n n n 1010 configuration read n y y y (type 0 only) 1011 configuration write y (type 1 only) y y y 1100 memory read multiple y y y y 1101 dual address cycle y y y y 1110 memory read line y y y y 1111 memory write and invalidate y y y y as indicated in table 4-1, the following commands are not supported by PI7C21P100: ? PI7C21P100 never initiates a transaction with a reserved command code and, as a target, PI7C21P100 ignores reserved command codes. ? PI7C21P100 does not generate interrupt acknowledge transactions. PI7C21P100 ignores interrupt acknowledge transactions as a target. ? PI7C21P100 does not respond to special cycle transactions. PI7C21P100 cannot guarantee delivery of a special cycle transact ion to downstream buses because of the broadcast nature of the special cycle command and the inability to control the transaction as a target. to generate special cycle transactions on other buses, either upstream or downstream, type 1 configuration write must be used.
PI7C21P100 2-port pci-x bridge advance information page 23 of 77 june 10, 2005 revision 1.06 4.2 write transactions write transactions are treated as posted wr ite, delayed/split (pci-x), or immediate write transactions. table 4-2 shows the method of forwarding used for each type of write operation. table 4-2 write transaction forwarding type of transaction type of forwarding memory write posted memory write and invalidate posted memory write block (pci-x) posted i/o write delayed / split (pci-x) type 0 configuration write immediate on the primary bus. delayed / split (pci-x) on the secondary bus. type 1 configuration write delayed / split (pci-x) 4.2.1 memory write transactions posted write forwarding is used for ?memor y write?, ?memory write and invalidate?, and ?memory write block? transactions. when PI7C21P100 determines that a memory write transaction is to be forwarded across the bridge, PI7C21P100 asserts devsel# with medium decode timing and trdy# in the next cycle, provided that enough buffer space is av ailable in the posted memory write queue for the address and at least one dword of data. under this condition, PI7C21P100 accepts write data without obtaining access to the target bus. the pi7c21 p100 can accept one dword of write data every pci clock cycle. that is, no target wait state is inserted. the write data is stored in an internal posted write buffers and is subsequently delivered to the target. the PI7C21P100 continues to accept write data until one of the following events occurs: ? the initiator terminates the transactio n by de-asserting frame# and irdy#. ? an internal write address bou ndary is reached, such as a cache line boundary or an aligned 4kb boundary, depending on the transaction type. ? the posted write data buffer fills up. when one of the last two events occurs, the PI7C21P100 returns a target disconnect to the requesting initiator on this data phase to terminate the transaction. once the posted write data moves to the head of the posted data queue, PI7C21P100 asserts its request on the target bus. this can occur while PI7C21P100 is still receiving data on the initiator bus. when the grant for th e target bus is received and the target bus is detected in the idle condition, PI7C21P100 asserts frame# and drives the stored write address out on the target bus. on the following cycle, PI7C21P100 drives the first dword of write data and continues to transfer write data until all write data corresponding to that transaction is delivered, or until a target termination is received . as long as write data exists in the queue, PI7C21P100 can drive one dword of write data in each pci clock cycle; that is, no master wait states are inserted. if write data is flow ing through PI7C21P100 and the initiator stalls, PI7C21P100 will signal the last data phase for the current transaction at the target bus if the queue empties. PI7C21P100 will restart the follo w-on transactions if the queue has new data.
PI7C21P100 2-port pci-x bridge advance information page 24 of 77 june 10, 2005 revision 1.06 PI7C21P100 ends the transaction on the target bus when one of the following conditions is met: ? all posted write data has been delivered to the target. ? the target returns a target disconnect or target retry (PI7C21P100 starts another transaction to deliver the rest of the write data). ? the target returns a target abort (PI7C21P100 discards remaining write data). ? the master latency timer expires, and PI7C21P100 no longer has the target bus grant (PI7C21P100 starts another transaction to deliver remaining write data). 4.2.1.1 pci-x to pci-x when both buses are operating in the pci-x mode, PI7C21P100 passes the memory write command that it receives to the destination interf ace along with the originating byte count and transaction id. PI7C21P100 attempts to transfer a memory write command when the transaction ends or a 128-byte boundary is crossed. as long as there is at least 128-byte of data in the data buffer or the end of transf er remains from the pci-x memory write command when a 128-byte boundary is crossed, the transfer will continue . if a transaction is disconnected on the destination interface in the middle of a continuing transfer, the byte count and address are updated and the transaction is pr esented again on the destination interface. if a transaction is disconnected in the middle of a co ntinuing transfer on th e originating interface, the originator must present th e transaction again with the updated byte count and address. 4.2.1.2 pci to pci when both buses are oper ating in conventional pci mode, the bridge passes the memory write command that it receives to the destination inte rface, unless PI7C21P100 is disconnected in the middle of a memory write and invalidate and is not on a cache line boundary. if this happens, the command will continue as a memo ry write when PI7C21P100 attempts to reconnect. PI7C21P100 attempts to transfer a memory write command when the transaction ends or a 128-byte boundary is crossed. as long as a 128-byte buffer is full or the end of transfer remains from the memory write comma nd when a 128-byte boundary is crossed, the transfer will continue. 4.2.1.3 pci to pci-x when the originating bus is operating in the conventional pci mode and the destination bus is operating in the pci-x mode, PI7C21P100 must buffer memory write transactions from the conventional pci interface and count the number of bytes to be forwarded to the pci-x interface. if the conventional pci transaction uses the memory write command and some byte enables are not asserted, PI7C21P100 must use the pci-x memory write command. if the conventional pci command is memory write and all byte enables are asserted, PI7C21P100 will use the pci-x memory write command. if the conventional transaction uses the memory write and invalidate command, PI7C21P100 uses the pci-x memory write block command. PI7C21P100 attempts to transf er the write data on the pc i-x interface as soon as the transaction ends or a 128-byte boundary is crossed. writes greater than 128 bytes are possible only if more than one 128-byte sector fills up before the write operation is issued on the pci- x interface.
PI7C21P100 2-port pci-x bridge advance information page 25 of 77 june 10, 2005 revision 1.06 4.2.1.4 pci-x to pci when the originating bus is operating in the pci-x mode and the destination bus is operating in the conventional pci mode, PI7C21P100 uses the pci conventional memory write command for both the pci-x memory write and pci-x memory write block commands. PI7C21P100 attempts to transf er write data on th e conventional pci interface when the pci-x data crosses a 128-byte boundary or the end of the pci-x transfer occurs. as long as a 128- byte buffer is full, or the end of transf er remains from the pci-x memory write command when a 128-byte boundary is crossed, the tr ansfer will continue on the conventional pci interface. 4.2.2 delayed/split write transactions delayed/split write forwarding is used for i/o write transactions, type 1 configuration write transactions, and type 0 conf iguration write transactions. delayed/split write forwarding transactions are retried on the originating bus, completed on the destination bus (if necessary), and then co mpleted on the originating bus. for dword transactions, PI7C21P100 uses delayed transactions in conventional pci mode and split requests in pci-x mode. only one request queue entry is allowed for either delayed or split write transactions. 4.2.3 immediate write transactions PI7C21P100 considers type 0 configuration writes on the primary bus meant for the bridge as immediate write transactions for the bridge. PI7C21P100 will execute the transaction and indicate its completion by accepting the dword of data immediately. 4.3 read transactions read transactions are treated as delayed read for conventional pci mode, split read for pci-x mode, or immediate read. table 4-3 shows the read behavior. table 4-3 read transactin handling type of transaction type of handling memory read delayed memory read line delayed memory read multiple delayed memory read dword (pci-x mode) split (pci-x mode) memory read block (pci-x mode) split (pci-x mode) i/o read delayed/split (pci-x) type 0 configuration read immediate on the primary bus, delayed/split (pci-x mode) on the secondary bus type 1 configuration read delayed/split (pci-x mode)
PI7C21P100 2-port pci-x bridge advance information page 26 of 77 june 10, 2005 revision 1.06 4.3.1 memory read transactions memory data is transferred from the originating side of PI7C21P100 to the destination side using pci memory read, memory read line, memory read multiple, pci-x memory read dword, and pci-x memory read block transac tions. all memory read transactions are either delayed or split on the originating side of PI7C21P100 depending on the mode of the originating side. 4.3.1.1 pci-x to pci-x no translation is needed for these transactions. the amount of data that is fetched is controlled by the downstream and upstream split transaction control register. the split transac tion capacity and split transaction commitment limit fields control how much data is requested at any one time. 4.3.1.2 pci to pci no translation is needed for these transactions. memory read ? fetches only the reques ted dword if the command targets a non- prefetchable memory space. bits [25:24] offset 40h and bits [9:8] offset 40h control the mode of prefetching for memory read transactions in the prefetchable range on the secondary and primary bus respectively. the default is up to one cache line will be prefetched. memory read line ? bits [23:22] offset 40h and bits [7:6] offset 40h control the mode of prefetching for memory read line transactions in the prefetchable range on the secondary and primary bus respectively. the default is up to one cache line will be prefetched. memory read multiple ? bits [21:20] offset 40h and bits [5:4] offset 40h control the mode of prefetching for memory read multiple transacti ons in the prefetchable range on the secondary and primary bus respectively. the default is a full prefetch, limited to the value set by bits [14:12] offset 40h. the default value is 512 bytes, or an entire read buffer. 4.3.1.3 pci to pci-x PI7C21P100 must translate the conventional pci memory read command to either the memory read dword or the memory read block pci-x command. if the conventional pci memory read command targets no n-prefetchable memory space, the command is translated into a memory read dword. in any other instance, the conventional pci memory read command gets translated into a memory read block pci-x command. bits [25:24] offset 40h and bits [9:8] offset 40h control the mode of pr efetching for memory read transactions in the prefetchable range on the secondary and primary bus respectively. the default is up to one cache line will be prefetched. th e default is up to one cache line will be prefetched. PI7C21P100 translates the conve ntional pci memory read line command to the memory read block pci-x command. bits [23:22] offset 40h and bits [7:6] offset 40h control the mode of prefetching for memory read line transactions in the prefetchable range on the secondary and primary bus respectively. the default is up to one cache line will be prefetched.
PI7C21P100 2-port pci-x bridge advance information page 27 of 77 june 10, 2005 revision 1.06 PI7C21P100 must translate the conventional pci memory read multiple command to the memory read block pci-x command. bits [21:20] offset 40h and bits [5:4] offset 40h control the mode of prefetching for memo ry read multiple transactions in the prefetchable range on the secondary and primary bus resp ectively. the default is a full prefetch, limited to the value set by bits [14:12] offset 40h. the default value is 512 bytes, or an entire read buffer. using a value greater than this is possible, but it may be constrained by the setting of the split transaction commitment limit value in the upst ream or downstream split transaction register, since the target bus is in pci-x mode. data fetching operations will be disconnected at all 1mb boundaries. 4.3.1.4 pci-x to pci PI7C21P100 translates pci-x memory r ead dword commands into conventional pci memory read commands. PI7C21P100 translates a pci-x memory read block command into one of three conventional pci memory read commands based on the byte count and starting address. if the starting address and byte count ar e such that only a sing le dword (or less) is being read, the conventional pci transaction uses the memory read command. if the pci-x transaction reads more than one dword, but do es not cross a cache line boundary (indicated by the cache line size register in the co nventional configurati on space header), the conventional transaction uses the memory r ead line command. if the pci-x transaction crosses a cache line boundary, the conventional transaction uses the memory read multiple command. if a disconnect occurs before the byte count of the pci-x memory read block command is exhausted, the PI7C21P100 continues to issue the command until all the bytes in the count are received. pi7c21p1 00 disconnects once th e buffer is filled and prefetches more data as 128-byte sectors of the buffer become free when split completion data is returned to the originator, until the byte count is exhausted. 4.3.2 i/o read the i/o read command is not translated and fetches a dword of data. the command will either be split in the pci-x mode or delayed in the conventional pci mode. 4.3.3 configuration read 4.3.3.1 type 1 configuration read the type 1 configuration read command is only accepted on the primary interface. the command will either be split in the pci-x mode or delayed in the conventional pci mode. 4.3.3.2 type 0 configuration read the type 0 configuration read command is accep ted on either the pr imary or secondary interface. the command returns immediate data on the primary interf ace regardless of the interface mode. on the secondary interface the command is treated either as a split transaction in pci-x mode or as a delayed transaction in the pci mode.
PI7C21P100 2-port pci-x bridge advance information page 28 of 77 june 10, 2005 revision 1.06 4.3.4 non-prefetchable and dword reads a non-prefetchable read transaction is a re ad transaction in which PI7C21P100 requests exactly one dword from the target and disconnects the initiator after delivering that one dword of read data. unlike prefetchable read transactions, PI7C21P100 forwards the read byte enable information for the data phase. non-prefetchable behavior is used for i/o, configuration, memory read tr ansactions that fall into the nonprefetchable memory space for pci mode, and all dword read transactions in pci-x mode. 4.3.5 prefetchable reads a prefetchable read transaction is a read tran saction where PI7C21P100 performs speculative reads, transferring data from the target before it is requested from the initiator. this behavior allows a prefetchable read tran saction to consist of multiple da ta transfers. fo r prefetchable read transactions, all byte enables are asserted for all data phases. prefetchable behavior is used for memory read line and memory read multiple transactions, as well as for memory read transactions that fall into prefetchable memo ry space and are allowed to fetch more than a dword. the amount of data that is prefetched depends on the type of transaction and the setting of bits in the primar y and secondary data buffering control registers in configuration space. the amount of prefetchin g may also be affected by the amount of free buffer space available in PI7C21P100, and by an y read address boundaries encountered. 4.3.5.1 pci-x to pci-x and pci-x to pci for pci-x to pci transactions, PI7C21P100 continues to generate data requests to the pci interface and keeps the prefetch buffer full until the entire amount of data requested is transferred. for pci-x to pci-x transactions, the split transaction commitment limit value contained in the upstream or downstream split transaction regi ster determines the operation. if the value is greater than or equal to the split transaction capacity (4kb) but less than 32kb, the maximum request amount is 512 bytes. larger transfers will be decomposed into a series of smaller transfers, until the original byte count has been satisfied. if the commitment limit value indicates 32kb or more, the original requ est amount is used and decomposition is not performed. if the original request is broken into smaller requests the bridge waits until the previous completion has been totally received before a new request is issued. this ensures that the data does not get out of order and that two requests with the same sequence id are not issued. in either case, the bridge generates a new requester id for each request passed through the bridge. 4.3.5.2 pci to pci the method used for transfers in pci-to-pci mode is user defined in the primary and secondary data buffering control registers. these registers have bits for memory read to prefetchable space, memory read line, and me mory read multiple transactions. for memory read, the bits select whether to read a dword, read to a cache line boundary, or to fill the prefetch buffer. for memory read line and memory read multiple transactions, the bits select whether to read to a cache line boundary or to f ill the prefetch buffer. in all cases, if the bits
PI7C21P100 2-port pci-x bridge advance information page 29 of 77 june 10, 2005 revision 1.06 are selected to fill the prefetch buffer, the maximum amount of da ta that is requested on the target interface is controllable by the setting of the maximum memory read byte count bits of the primary and secondary data buffering control registers. when more than 512 bytes are requested, the bridge fetches data to fill the buffer and then fetches more data to keep the buffer filled as sectors (128 bytes) are emptied and become free to use again. 4.3.5.3 pci to pci-x the method used for transfers in the pci to pci-x mode is similar to transfers in the pci-to- pci mode, except that the maximum request am ount may be additionally constrained by the setting of the split transaction commitment limit value in the upstream or downstream split transaction register. the only other difference is that prefetching will not stop when the originating master disconnects. prefetching will only stop when all of the requested data is received. 4.3.6 dynamic prefetch (convent ional pci mode only) for prefetchable reads described in the previous section, the prefetching length is normally predefined and cannot be changed once it is set. this may cause some inefficiency as the prefetching length determined could be larger or smaller than the actual data being prefetched. to make prefetching more efficient, pi7c21p 100 incorporates dynamic prefetching control logic. this logic regulates the different pci memory read commands (mr ? memory read, mrl ? memory read line, and mrm ? memory read multiple) to improve memory read burst performance. PI7C21P100 tracks every memory read burst transaction and tallies the status. by using the status information, PI7C21P100 can determine to increase, reduce, or keep the same cache line length to be prefetched. over time, PI7C21P100 can better match the correct cache line setting to the length of data being re quested. the dynamic prefetching control logic is set with bits[3:2] offset 48h. 4.4 configuration transactions configuration transactions are used to initialize a pci system. every pci device has a configuration space that is accessed by configuration commands . all registers are accessible in configuration space only. in addition to accepting configuration transactions for initia lization of its own configuration space, the PI7C21P100 also forw ards configuration transactions for device initialization in hierarchical pci systems, as well as for special cycle generation. to support hierarchical pci bus systems, tw o types of configura tion transactions are specified: type 0 and type 1. type 0 configuration transactions are issued when the intended target resides on the same pci bus as the initiator. a type 0 configuration tr ansaction is identified by the configuration command and the lowest two bits of the address set to 00b. type 1 configuration transactions are issued when the intended target resides on another pci bus, or when a special cycle is to be generated on another pci bus. a type 1 configuration command is identified by the configuration command and the lowest two address bits set to 01b.
PI7C21P100 2-port pci-x bridge advance information page 30 of 77 june 10, 2005 revision 1.06 the register number is found in both type 0 and type 1 formats and gives the dword address of the configuration regi ster to be accessed. the function number is also included in both type 0 and type 1 formats and indicates which function of a multifunction device is to be accessed. for single-function devices, this va lue is not decoded. the addresses of type 1 configuration transaction include a 5-bit field designating the device number that identifies the device on the target pci bus that is to be accessed. in addition, the bus number in type 1 transactions specifies the pci bus to which the transaction is targeted. 4.4.1 type 0 access to PI7C21P100 the configuration space is accessed by a type 0 configuration transaction. the configuration space can be accessed from the primary or seco ndary interface. s_idse l should be tied low if access is not required from the secondary interface. on the primary interface, PI7C21P100 responds to a type 0 configuration transaction by accepting the transaction when the following conditions are me t during the address phase: ? p_cbe[3:0]# indicates a conf iguration write or config uration read transaction ? the two lowest address b its on p_ad[1:0] are 00 ? p_idsel is asserted ? bit[2] offset 44h (miscellaneous control register) is 0 on the secondary interface, pi7c 21p100 responds to a type 0 configuration transaction by accepting the transaction when the following conditions are me t during the address phase: ? s_cbe[3:0]# indicates a conf iguration write or config uration read transaction ? the two lowest address b its on s_ad[1:0] are 00 ? s_idsel is asserted the function number is not decoded since the bridge is a single-function device. all configuration transactions to the bri dge are handled as dword operations. 4.4.2 type 1 to type 0 conversion type 1 configuration transactions are used specifically for devi ce configuration in a hierarchical pci/pci-x bus system. a bridge is the only type of device that should respond to a type 1 configuration command. type 1 configuration commands are used when the configuration access is intended for a pci/pci-x device that resides on a bus other than the one where the type 1 transaction is generated. PI7C21P100 performs a type 1 to type 0 translation when the type 1 transaction is generated on the primary interface and is inte nded for a device attach ed directly to the secondary interface. PI7C21P100 must convert the configuration command to a type 0 format so that the secondary bus device can respond to it. type 1 to type 0 translations are performed only in the downstream direction. PI7C21P100 responds to a type 1 configuration transaction and translates it into a type 0 transaction on the secondary interface when the following conditions are met during the address phase: ? the lowest two address bits on p_ad[1:0] are 01b.
PI7C21P100 2-port pci-x bridge advance information page 31 of 77 june 10, 2005 revision 1.06 ? the bus number in address field p_ad[23:16] is equal to the value in the secondary bus number register in configuration space. ? p_cbe[3:0]# is a configuration read or configuration write transaction. when PI7C21P100 translates the type 1 transac tion to a type 0 transaction on the secondary interface, it performs the following translations to the address: ? sets the lowest two address bits on s_ad[1:0] to 00. ? decodes the device number and drives the bit pattern specified in table 4-4 on s_ad[31:16] for the purpose of asserting the device?s idsel signal. ? sets s_ad[15:11] to 0 if the secondary bus is operating in conventional pci mode (device number is passed through unchanged in pci-x mode) ? leaves unchanged the function number and register number fields. PI7C21P100 asserts a unique address line base d on the device number. these address lines may be used as secondary bus idsel signals. the mapping of the address lines depends on the device number in the address bits p_ad [15:11] for type 1 transactions. table 4-4 presents the mapping that PI7C21P100 uses. table 4-4 device number to idsel device number p_ad[15:11] secondary idsel s_ad[31:16] 0h 00000 0000 0000 0000 0001 1h 00001 0000 0000 0000 0010 2h 00010 0000 0000 0000 0100 3h 00011 0000 0000 0000 1000 4h 00100 0000 0000 0001 0000 5h 00101 0000 0000 0010 0000 6h 00110 0000 0000 0100 0000 7h 00111 0000 0000 1000 0000 8h 01000 0000 0001 0000 0000 9h 01001 0000 0010 0000 0000 ah 01010 0000 0100 0000 0000 bh 01011 0000 1000 0000 0000 ch 01100 0001 0000 0000 0000 dh 01101 0010 0000 0000 0000 eh 01110 0100 0000 0000 0000 fh 01111 1000 0000 0000 0000 10h ? 1eh 10000 ? 11110 0000 0000 0000 0000 1fh 11111 0000 0000 0000 0000 or, may convert to a special cycle transaction described in section 4.4.4 PI7C21P100 forwards type 1 to type 0 configuration read or write transactions as delayed transactions in pci mode or as split transactions in pci-x mode. 4.4.3 type 1 to type 1 forwarding type 1 to type 1 transaction forwarding prov ides a hierarchical configuration mechanism when two or more levels of pci-to-pci bridges are used. when PI7C21P100 detects a type 1 configuration transaction intended for a pci/pci-x bus downstream from the secondary interface, PI7C21P100 forwards the transaction unchanged to the secondary interface. ultimately, this transac tion is translated to a type 0 configuration command or to a special cycle transaction by a downstream pci bridge. downstream type 1 to type 1 forwarding occurs when the following conditions are met during the address phase:
PI7C21P100 2-port pci-x bridge advance information page 32 of 77 june 10, 2005 revision 1.06 ? the lowest two address bits on p_ad[1:0] are equal to 01b. ? the bus number falls in the range defined by the lower limit (exclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. ? p_ad[1:0] is a configuration read or configuration wr ite transaction. PI7C21P100 also supports type 1 to type 1 forwarding of configuration write transactions upstream to support upstream special cycle ge neration. all upstream type 1 configuration read commands are ig nored by PI7C21P100. PI7C21P100 forwards type 1 to type 1 configuration read and write transactions as delayed transactions in the pci mode and as split transactions in pci-x mode. 4.4.4 special cycles the type 1 configuration mechanism is used to generate special cycle transactions in hierarchical pci/pci-x systems. special cycle transactions can be generated from type 1 configuration write transactions in either the upstream or the downstream direction. PI7C21P100 initiates a special cycle on the target bus when a type 1 configuration write transaction is detected on the initiating bus and the following conditions are met during the address phase: ? the lowest two address bits on ad[1:0] are equal to 01b. ? the device number in address bits ad[15:11] is equal to 11111b. ? the function number in address bits ad[10:8] is equal to 111b. ? the register number in address bits ad[7:2] is equal to 000000b. ? the bus number is equal to the value in the secondary bus number register for downstream transactions or equal to the value in the primary bus number register for upstream transactions. ? the bus command on cbe is a configuration write command. when PI7C21P100 initiates the transaction on the target interface, the bus command is changed from configuration write to special cycle. devices that use special cycles ignore the address and decode only the bus command. the data phase contains the special cycle message. the transaction is forwarded as a de layed transaction in pci mode and as a split transaction in pci-x mode. once the transaction is completed on the target bus through detection of the master abort condition, PI7C21P100 completes the transaction on the initiating bus by accepting the retry on the delaye d command in pci mode or by generating a completion message in pci-x mode. special cycl es received by pi7c21p1 00 as a target are ignored. 5 transaction ordering to maintain data coherency and consistency, PI7C21P100 complies with the ordering rules set forth in the pci local bus specification, revision 2.2 for pci mode, and pci-x addendum to the pci local bus specification, revision 1.0a for pci-x mode. this chapter describes the ordering rules that control transaction forwarding across PI7C21P100.
PI7C21P100 2-port pci-x bridge advance information page 33 of 77 june 10, 2005 revision 1.06 5.1 general ordering guidelines independent transactions on primary and secondary buses have a relationship only when those transactions cross PI7C21P100. the following general ordering guidelines govern transactions crossing PI7C21P100: ? requests terminated with target retry can be accepted and completed in any order with respect to other transactions that have been terminated with target retry. if the order of completion of delayed or split requests is important, the initiator should not start a second delayed or split transaction until the first one has been completed. if more than one delayed or split transaction is initiated, th e initiator should repeat all retried requests, using some fairness algorithm. repeating a delayed or split transaction cannot be contingent on completion of another delayed transaction. otherwise, a deadlock can occur. ? write transactions flowing in one direction have no ordering requirements with respect to write transactions flowing in the other di rection. PI7C21P100 can accept posted write transactions on both interfaces at the sa me time, as well as initiate posted write transactions on both interfaces at the same time. ? the acceptance of a posted memo ry or memory write transaction as a target can never be contingent on the completion of a non-locked, non-posted transaction as a master. this is true for PI7C21P100 and must also be true for other bus agents. otherwise, a deadlock can occur. ? PI7C21P100 accepts posted write transactions, regardless of the state of completion of any delayed transactions being forwarded across PI7C21P100. 5.2 ordering rules table 5-1 summary of transaction ordering in pci mode and table 5-2 show the ordering relationships of all the transactions and refers by number to the ordering rules that follow. table 5-1 summary of transaction ordering in pci mode pass posted write delayed read request delayed write request delayed read completion delayed write completion posted write no yes yes yes yes delayed read request no yes yes yes yes delayed write request no yes no yes yes delayed read completion no 1 yes yes yes yes delayed write completion no yes yes yes no 1. if the relaxed ordering bit is set in pci to pci mode , or the enable relaxed ordering bit in the primary and/or secondary data buffering control regist ers is set in any other mode, read completions can pass memory writes. table 5-2 summary of transaction ordering in pci-x mode pass memory write split read request split write request split read completion split write completion posted write no yes yes yes yes delayed read request no yes yes yes yes delayed write request no yes no yes yes
PI7C21P100 2-port pci-x bridge advance information page 34 of 77 june 10, 2005 revision 1.06 pass memory write split read request split write request split read completion split write completion delayed read completion no 1 yes yes yes 2 yes delayed write completion no yes yes yes no 1. if the relaxed ordering bit is set in pci-x to pci-x mode, or the enable relaxed ordering bit in the primary and/or secondary data buffering control regist ers is set in any other mode, read completions can pass memory writes. 2. split read completions with the same se quence id must remain in address order. 6 clocks this chapter provides information about the clocks. 6.1 primary and secondary clock inputs the primary and secondary interface on PI7C21P100 each has its own clock input pin. p_clk is the clock input for the primary and s_clk is the input for the secondary (s_clk also controls the internal arbiter). the two clocks are independent of each other and may be run synchronously or asynchronously to each other at any value supported by the pci or pci- x specifications. each interface utilizes a sepa rate internal pll (phase-locked loop) circuit when running in pci-x mode. in pci mode, the pll?s are bypassed, allowing for any clock frequency from 0 to 66mhz. if the primary is running at 133mhz in pci-x mode, then the secondary is limited to a minimum frequency of 33mhz in conventional pci mode. to run the secondary slower, the primary frequency needs to be reduced so that the ratio does not exceed 4:1. 6.2 clock jitter PI7C21P100 tolerates a maximum of +/- 250ps of short term and long term jitter on the clock inputs. short term jitter is defined as the relationship between one clock edge to the next subsequent clock edge for one clock cycle, and long term jitter is the same relationship over many clock cycles. 6.3 mode and clock freq uency determination 6.3.1 primary bus PI7C21P100 does not have i/o pins for the m66en or pcixcap signals on the primary bus. PI7C21P100 adjusts its internal configuration based on the initialization pattern it detects on p_devsel#, p_stop#, and p_trdy# at the rising edge of p_rst#. if the internal pll is being used (the bus is configured in the pci-x mode), a maximum of 100 s from the rising edge of p_rst# is required to lock the pll to the frequency of the clock supplied on the p_clk input.
PI7C21P100 2-port pci-x bridge advance information page 35 of 77 june 10, 2005 revision 1.06 6.3.2 secondary bus the secondary interface is capable of operating in either conventional pci mode or in pci-x mode. PI7C21P100 controls the mode and frequency for the secondary bus by utilizing a pull- up circuit connected to s_pc ixcap. there are two pull-up resistors in the circuit as recommended by the pci-x addendum. the first resistor is a weak pull-up (56k ohms) whose value is selected to set the voltage of s_pcixcap below its low threshold when a pci-x 66 device is attached to the secondary bus. the second resistor is a strong pull-up, externally wired between s_pcixcap and s_pc ixcap_pu. the value of the resistor (1k ohm) is selected to set the voltage of s_pcixcap above its high threshold when all devices on the secondary are pci-x 66 capable. to detect the mode and frequency of the secondary bus, s_pcixcap_pu is initially disabled and PI7C21P100 samples the value on s_pcixcap. if PI7C21P100 sees a logic low on s_pcixcap, one or more devices on the secondary have either pulled the signal to ground (pci-x 66 capable) or tied it to ground (only capable of conventional pci mode). to differentiate between the two conditions, PI7C21P100 then enables s_pcixcap_pu to put the strong pull-up into the circuit. if s_pcixcap remains at a logic low, it must be tied to ground by one or more devices, and the bus is initialized to conventional pci mode. if s_pcixcap_pu can be pulled up, one or more devices are capable of only pci-x 66 operation so the bus is initialized to pci-x 66 mode. if PI7C21P100 sees a logic high on s_pcixcap, then all devi ces on the secondary bus are capable of pci-x 133 operation. PI7C21P100 then samples s_sel100 to distinguish between the 66-100 mhz and the 100-133 mhz clock frequency ranges. if PI7C21P100 sees logic high on s_sel100, the secondary bus is initialized to pci-x 100 mode. if the value is low, pci-x 133 is initialized. these two ranges allow adjustment of the clock frequency to account for bus loading conditions. there is no pin for m66en for the secondary interface on PI7C21P100 because the internal pll is bypassed in conventional pci mode. s_clk is used directly, eliminating the need to distinguish between conventional pci 33 and conventional pci 66. table 6-1 programmable pull-up circuit
PI7C21P100 2-port pci-x bridge advance information page 36 of 77 june 10, 2005 revision 1.06 6.3.3 clock stability to comply with pci and pci-x architecture specifications, the bu s clock must be stable and running at the designated frequency for at leas t 100us after deassertion of the bus reset. s_clk_stable is used to determine and detect when s_clk has become stable. during a bus reset, PI7C21P100 will wait for the asser tion of s_clk_stable before determining the mode and frequency. PI7C21P100 is expecting no more than one transition on the s_clk_stable input from the ?not stable? to the ?stable? state. s_clk_stable input may be tied high if the secondary clock input is known to be always stable prior to the deassertion of the primary bus reset signal or the secondary bus reset bit of the bridge control register. examples of sources for s_clk_st able are lock indicators on circuits that employ pll?s or ?power good? indicators. 6.3.4 driver impedance selection the output drivers on PI7C21P100 are capable of two different output impedances, 40 ohm output impedance and a 20 ohm. the output impedance for the primary and secondary interfaces is separately controlled. pi7c21p1 00 selects a default impedance value at the deassertion of the bus reset based on the bus mode and frequency. if a bus is configured to be in pci-x 133 mode, it is assumed that the bus will have fewer devices and have a higher impedance. in this case, the drivers utilize the 40 ohm output impedance mode. the 20 ohm output impedance mode is utilized for all other pci-x and all pci configurations, assuming that the bus is more heavily loaded and has lower impedance. some applications do not follow these assumptions so two control signal s are provided; p_drvr for the primary and s_drvr for the secondary. when these inputs are pulled high, PI7C21P100 will change the output impedance of the drivers on their respective interfaces to the opposite state than was assumed by default, as shown in table 6-2. the driver mode may not be changed dynamically, but can be changed during each bus reset. table 6-2 driver impedance selection primary bus mode default driver mode (p_drvr=0) driver mode if (p_drvr=1) secondary bus mode default driver mode (s_drvr=0) driver mode if (s_drvr=1) conventional pci 20 ohm 40 ohm conventional pci 20 ohm 40 ohm pci-x 66 20 ohm 40 ohm pci-x 66 20 ohm 40 ohm pci-x 100 20 ohm 40 ohm pci-x 100 20 ohm 40 ohm pci-x 133 20 ohm 20 ohm pci-x 133 40 ohm 20 ohm 7 reset the primary and secondary interface each have their own asynchronous reset signal used at power-on and at other times to put PI7C21P100 into a known state. the reset signal on the primary (p_rst#) is an input pin, while the reset signal on the secondary (s_rst#) is an output pin driven by PI7C21P100.
PI7C21P100 2-port pci-x bridge advance information page 37 of 77 june 10, 2005 revision 1.06 7.1 primary interface reset when p_rst# is asserted, the following events occur: ? PI7C21P100 immediately tri-st ates all primary pci interface signals. s_ad[31:0] and s_cbe[3:0] are driven low on the secondary interface and other control signals are tri- stated. ? PI7C21P100 performs a chip reset. ? registers that have default values are reset. PI7C21P100 is not accessible duri ng p_rst#. after p_rst# is deasserted in pci-x mode, PI7C21P100 remains inaccessible fo r 100us to enable the internal pll to lock to its target frequency. in conventional pci mode, PI7C21P100 is held in reset 7 pci clocks after the deassertion of p_rst#. 7.2 secondary interface reset PI7C21P100 is responsible for driving the secondary bus reset signals, s_rst#. pi721p100 asserts s_rst# when any of the following conditions are met: signal p_rst# is asserted. signal s_rst# remains asserted as long as p_rst# is asserted and does not de-assert until p_rst# is de-asserted. the secondary reset bit in the bridge control register is set. signal s_rst# remains asserted until a configuration write operation clears the secondary reset bit. several things must occur at or prior to the de-assertion of s_rst#. once p_rst# is de-asserted or the secondary bus reset bit is changed from 1 to 0, PI7C21P100 will wait for the s_clk_stable signal to be asserted before proceeding. s_clk must be stable at a frequency within the bus capability limits prio r to the assertion of s_clk_stable. since the pci local bus specification requ ires that the bus clock be stable for at least 100us prior to the de-assertion of the bus reset, s_clk_stable se rves as a gate to a timer that ensures that this requirement is met. during this time delay period, the secondary bus mode and frequency is determined through the programmable pull-up circuit. this process may include up to 80us for the capacitive load on s_pcixcap to be charged. by the time the 100us timer expires, the bus mode and frequency will have been determined. the s_rst# signal is then de-asserted a minimum of ten secondary bus pci clock cycles later. when the secondary bus is operating in pci-x mode, an internal pll is used to source the clock tree for the secondary clock domain inside PI7C21P100. the appropriate range and tuning bits for the pll are set once the mode and frequency are determined, and an internal pll reset signal is deactivated to allow the pll to begin locking to the s_clk input frequency. the pll requires an allowance of 100us to accomplish this frequency lock. an internal reset is held on the logic in the secondary clock domain until this time period has elapsed. while the internal reset is active, PI7C21P100 will not respond to any secondary bus transactions. when the secondary bus is operating in pci mode, the internal pll for the secondary interface is not used. the internal p ll reset remains activated, keeping the pll in the bypass mode, and the internal logic reset is held for 5 additional secondary pci clock cycles.
PI7C21P100 2-port pci-x bridge advance information page 38 of 77 june 10, 2005 revision 1.06 table 7-1 delay times for de-assertion of s_rst# conventional pci pci-x 66 pci-x 100 pci-x 133 t pirstdly 7 primary clock cycles 6678 primary clock cycles 100us ? 133us 13350 primary clock cycles 133us ? 200us 13350 primary clock cycles 100us ? 133us t xcap 6675 primary clock cycles 6675 primary clock cycles 100us ? 133us 13347 primary clock cycles 133us ? 200us 13347 primary clock cycles 100us ? 133us t srstdly 11 secondary and 7 primary clock cycles 11 secondary and 7 primary clock cycles 11 secondary and 7 primary clock cycles 11 secondary and 7 primary clock cycles t sirstdly 16 secondary clock cycles 6687 secondary clock cycles 100us ? 133us 13350 secondary clock cycles 133us ? 200us 13350 secondary clock cycles 100us ? 133us note: primary and secondary clock cycles refer to cloc k cycles whose period is determined by the p_clk and s_clk inputs. table 7-2 de-assertion of s_rst# 7.3 bus parking & bus wi dth determination bus parking refers to driving the ad[31:0], cbe[3:0], and par lines to a known value while the bus is idle. in general, the device implementing the bus arbiter is responsible for parking the bus or assigning another device to park the bus. a device parks the bus when the bus is idle, its bus grant is asserted, and the device?s request is not asserted. the ad[31:0], cbe[3:0], and par signals are driven low after assertion of s_rst#. PI7C21P100 will assert s_req64# for at leas t 10 pci clock cycles to allow devices to determine whether they are connected on a 64-bit bus or 32-bit bus. 7.4 secondary device masking secondary devices can be masked through configuration or power strapping of the secondary bus private device mask register. the process of converting type 1 conf iguration transactions to type 0 configuration transactions is modified by the contents of the secondary bus private device mask register. a configuration transaction that targets a device masked by this register is routed to device 15. secondar y bus architectures which are de signed to support masking of
PI7C21P100 2-port pci-x bridge advance information page 39 of 77 june 10, 2005 revision 1.06 devices should not implement a device number 15 (i.e., s_ad(31)). the device mask bit options (device numbers 1, 4, 5, 6, 7, 9, and 13) defined by PI7C21P100 allow architectures to support private device groupings that use a single or multiple interrupt binding. 7.5 address parity errors PI7C21P100 checks address parity for all transactions on both buses, for all address and all bus commands. when PI7C21P100 detects an addres s parity error, the transaction will not be claimed and will be allowed to terminate with a ma ster abort. the result of an address parity error will be controlled by the parity error re sponse bits in both the command and bridge control registers. 7.6 optional base address register the 64 bit base address register located in th e configuration register at offsets 10h and 14h can optionally be used to acquire a 1 mb memory region at system initialization. PI7C21P100 uses this register to claim an additional pref etchable memory region for the secondary bus. when used with the secondary device masking, this allows for the acquisition of memory space for private devices that are not othe rwise viewable by the system software. this 64 bit base address register and the memory space defined by it are enabled by the bar_en. when bar_en is pulled low, this register location returns zeros for reads and cannot be written. when bar_en is pulled hi gh, the upper memory ba se address register and lower memory base address registers combin ed specify address bits 63:20 of a memory region. memory accesses on the primary bus are comp ared against this register, if address bits 63:20 are equal to bits 63:20 of the address defined by the combination of the lower memory base address register and the upper memory ba se address register, the access is claimed by PI7C21P100 and passed through to the seconda ry bus. memory accesses on the secondary bus are also compared against this register, if addr ess bits 63:20 are equal to bits 63:20 of the address defined by the combination of the lower memory base address register and the upper memory base address register, the access is ignored by the bridge. 7.7 optional configurat ion access from the secondary bus PI7C21P100 accepts type 0 conf iguration transactions when th e following conditions are met during the address phase: ? s_cbe[3:0]# indicates a conf iguration read or config uration write transaction ? s_ad[1:0] are 00 ? s_idsel is asserted applications that require access to the bridge configuration registers via the secondary bus may control the initialization sequence through th e p_cfg_busy pin and bit[2] offset 44h of the miscellaneous control register. when p_cfg_busy is pulled high, bit[2] offset 44h is set to 1b at power up and reset. this causes PI7C21P100 to retry type 0 configuration transactions on the primary bus that would otherwise be accepted. PI7C21P100 continues to retry these transactions until bit[2] offset 44h is set to 0b by a configuration write initiated on the secondary bus. this allows a device on the secondary bus to initialize the bridge and any private devices on the secondary bus without contention from devices accessing the bridge
PI7C21P100 2-port pci-x bridge advance information page 40 of 77 june 10, 2005 revision 1.06 through the primary bus. applications that do not requir e access to the bridge configuration registers via the secondary bus should pull bo th the s_idsel and p_cfg_busy pins low. 7.8 short term caching short term caching is a means to provide performance improvements where upstream devices are not able to stream data continuo usly to meet the prefetching needs of the PI7C21P100. when the master completes the trans action, the bridge is required to discard the balance of any data that was pr efetched for the master. to pr event performance impacts when dealing with target devices that can only stream data of 128 to 512 bytes before disconnecting, PI7C21P100 utilizes short term caching. this feature applies only when the secondary bus is operating in conventional pci mode and provides a time limited read data cache in which the bridge will no t discard prefetched read data after the request has been completed on the initiating bus. short term caching is an optional feature which is enabled by setting bit[8] and bit[15] offset b8h of the miscellaneous control register 2. when enabled, PI7C21P100 will not discard the additiona l prefetched data when the read transaction has been completed on the initiating bus. PI7C21P100 will continue to prefetch data up to the amount specified by bits [30:28] offset 40h of the secondary data buffering control register. should the initiator generate a new transaction requesting the previously prefetched data, PI7C21P100 will return that data. pi7c21p1 00 will discard the data approximately 64 secondary clocks after some of the data for a request has been returned to the initiator, and the initiator has not requested additional data. this feature applies to all secondary devices if enabled. system designers need to ensure that all attached devi ces have memory region(s) that are architected to be accessed by only one ma ster and that the additional prefetching will present data to the initiator in the same state as if the initial transaction were continued. this feature should only be used in system designs that are able to ensure that the data provided to the master has not been modified since the initial transaction.
PI7C21P100 2-port pci-x bridge advance information page 41 of 77 june 10, 2005 revision 1.06 8 configuration registers pci configuration defines a 64 dword space to define various attributes of PI7C21P100. 8.1 configuration register space map table 8-1 configuration space map bit number 31 ? 24 23 ? 16 15 ? 8 7 - 0 dword address device id vendor id 00h primary status primary command 04h class code revision id 08h bist header type primary latency timer cache line size 0ch lower memory base address 10h upper memory base address 14h secondary latency timer subordinate bus number secondary bus number primary bus number 18h secondary status i/o limit i/o base 1ch memory limit memory base 20h prefetchable memory limit prefetchable memory base 24h prefetchable base upper 32-bit 28h prefetchable limit upper 32-bit 2ch i/o limit upper 16-bit i/o base upper 16-bit 30h reserved capability pointer 34h expansion rom base address 38h bridge control interrupt pin interrupt line 3ch secondary data buffering control primary data buffering control 40h reserved miscellaneous control 44h reserverd extended chip control 2 extended chip control 1 48h reserved 4ch reserved arbiter mode 50h reserved arbiter enable 54h reserved arbiter priority 58h reserved serr# disable 5ch primary retry counter 60h secondary retry counter 64h reserved discard timer control 68h reserved retry and timer status 6ch reserved opaque memory enable 70h opaque memory limit opaque memory base 74h opaque memory ba se upper 32-bit 78h opaque memory limit upper 32-bit 7ch pci-x secondary status next capability pointer pci-x capability id 80h pci-x bridge status 84h secondary bus upstream split transaction 88h primary bus downstream split transaction 8ch power management capabilities next capabilities pointer power management id 90h pci-to-pci bridge support extension po wer management control and status 94h reserved 98h-ach secondary bus private device mask b0h reserved b4h reserved miscellaneous control 2 b8h reserved bch-ffh
PI7C21P100 2-port pci-x bridge advance information page 42 of 77 june 10, 2005 revision 1.06 8.1.1.1 signal type definition signal type definition ro read only rw read / write rwc read / write 1 to clear 8.1.2 vendor id register ? offset 00h bit function type description 15:0 vendor id ro identifies pericom as the vendor of this device. hardwired as 12d8h 8.1.3 device id register ? offset 00h bit function type description 31:16 device id ro identifies the device as PI7C21P100. hardwired as 01a7h. 8.1.4 command register ? offset 04h bit function type description 15:10 reserved ro reserved. returns 000000 when read. 9 fast back-to-back enable ro fast back-to-back control 0 : prohibits PI7C21P100 to initiate fa st back-to-back transactions on the primary this bit is ignored in pci-x mode. reset to 0 8 p_serr# enable rw system error control 0: disables the p_serr# driver on the primary 1: enables the p_serr# driver on the primary reset to 0 7 wait cycle control ro wait cycle control 0: address/data stepping is disa bled (primary and secondary) this bit is ignored in pci-x mode. returns 0 when read. 6 parity error response rw parity error response 0: PI7C21P100 may ignore any detected parity errors and continue normal operation 1: PI7C21P100 must take its normal action when a parity error is detected. reset to 0 5 vga palette snoop enable rw vga palette snoop control 0: ignore vga palette accesses on the primary 1: enables positive decoding response to vga palette writes on the primary with i/o address bits ad[9:0] equal to 3c6h, 3c8h, and 3c9h (inclusive of isa aliases; ad[15:10] are not decoded and may be any value. reset to 0 4 memory write and invalidate enable ro memory write and invalidate control 0: disables memory write and inva lidate transactions. PI7C21P100 does not generate memory write and invalidate transactions. this bit is ignored in pci-x mode. returns 0 when read. 3 special cycle enable ro special cycle control 0: PI7C21P100 does not respond as a target to special cycle transactions. returns 0 when read.
PI7C21P100 2-port pci-x bridge advance information page 43 of 77 june 10, 2005 revision 1.06 bit function type description 2 bus master enable rw bus master control 0: PI7C21P100 does not initiate memory and i/o transactions on the primary and disables responses to memory and i/o transactions on the secondary 1: enables PI7C21P100 to operate as a master on the primary for memory and i/o transactions forwarded from the secondary. in pci-x mode, PI7C21P100 is allo wed to initiate a split completion transaction regardless of the stat us of this bit. reset to 0 1 memory space enable rw memory space control 0: ignore memory transactions on the primary 1: enables responses to memory transactions on the primary reset to 0 0 i/o space enable rw i/o space control 0: ignores i/o transactions on the primary 1: enables responses to i/o transaction on the primary reset to 0 8.1.5 primary status register ? offset 04h bit function type description 31 detected parity error rwc detected parity error status 0: address or data parity erro r not detected by PI7C21P100 1: address or data parity e rror detected by PI7C21P100 reset to 0 30 signaled system error rwc signaled system error status 0: PI7C21P100 did not assert serr# 1: PI7C21P100 asserted serr# reset to 0 29 received master abort rwc received master abort status 0: transaction not terminated with a bus master abort 1: transaction terminated with a bus master abort reset to 0 28 received target abort rwc received target abort status 0: transaction not terminated with a target abort 1: transaction terminated with a target abort reset to 0 27 signaled target abort rwc signaled target abort status 0: target device did not terminate tr ansaction with a target abort 1: target device terminated transaction with a target abort 26:25 devsel# timing ro devesel# timing status 01: medium decoding. returns 01h when read. 24 data parity error rwc data parity error status 0: no data parity error detected 1: data parity error detected reset to 0 23 fast back-to-back capable ro fast back-to-back status 0: target not capable of decoding fa st back-to-back transactions in pci-x mode 1: target capable of decoding fast back-to-back transactions in conventional pci mode returns 0 in pci-x mode and 1 in conventional pci mode 22 reserved ro reserved. returns 0 when read. 21 66mhz capable ro 66mhz capable status 1: capable of 66mhz operation returns 1 when read. 20 capability list ro capability list 1: PI7C21P100 supports the capability list and offset 34h is the pointer to the data structure. returns 0 when read. 19:16 reserved ro reserved. returns 0000 when read.
PI7C21P100 2-port pci-x bridge advance information page 44 of 77 june 10, 2005 revision 1.06 8.1.6 revision id register ? offset 08h bit function type description 7:0 revision id ro specifies the revision of PI7C21P100. read as 0h 8.1.7 class code register ? offset 08h bit function type description 31:24 class code ro specifies the base cl ass code for PI7C21P100 identifying it as a bridge device according to pci specifications. read as 06h 23:16 sub class code ro specifies the sub-cl ass code identifying PI7C21P100 as a bridge device. read as 04h. 15:8 programming interface ro subtractive decoding not supported. read as 0h 8.1.8 cache line size register ? offset 0ch bit function type description 7:0 cache line size rw designates the cache line size for the system and is used when terminating memory write and i nvalidate transactions and when prefetching memory read transac tions. not used in pci-x mode. bit[7:6]: not supported and should be 00b bit[5]: if 1, then cache line size = 32 dwords bit[4]: if 1, then cache line size = 16 dwords bit[3]: if 1, then cache line size = 8 dwords bit[2]: if 1, then cache line size = 4 dwords bit[1:0]: not supported and should be 00b 8.1.9 primary latency timer ? offset 0ch bit function type description 15:11 primary latency timer rw desi gnates the upper 5 bits of the prim ary latency timer in pci clock units 10:8 primary latency timer ro desi gnates the lower 3 bits of the primary latency timer in pci clock units. returns 000 when read to force 8-cycl e increments for the latency timer. 8.1.10 header type register ? offset 0ch bit function type description 23 single function device ro returns 0 when read to designate single function device 22:16 pci-to-pci configuration ro returns 0000001 when read. 8.1.11 bist register ? offset 0ch bit function type description 31:24 bist ro bist not supported. returns 0 when read.
PI7C21P100 2-port pci-x bridge advance information page 45 of 77 june 10, 2005 revision 1.06 8.1.12 lower memory base address register ? offset 10h bit function type description 31:20 memory base address rw address bits[31:20] of the memory base address if bar_en is 1. if bar_en is 0, then this register is reserved and returns zeros when read. 19:4 reserved ro reserved. returns 00h when read 3 prefetchable indicator ro identifies the address ra nge defined by this register is prefetchable. returns 1 when read 2:1 decoder width ro indicates that this is the lower portion of a 64-bit register. returns 10b when read. 0 decoder type ro indicates that this regi ster is a memory decoder. returns 0 when read. 8.1.13 upper memory base address register ? offset 14h bit function type description 31:0 upper memory base address rw address bits[63:32] of the memory base address if bar_en is 1. if bar_en is 0, this register is reserved and returns zeros when read. 8.1.14 primary bus number register ? offset 18h bit function type description 7:0 primary bus number rw records the bus number of the pci segment that PI7C21P100 is connected to on the primary side. reset to 00h 8.1.15 secondary bus number register ? offset 18h bit function type description 15:8 secondary bus number rw records the bus number of the pci segment that PI7C21P100 is connected to on the secondary side. reset to 00h 8.1.16 subordinate bus number register ? offset 18h bit function type description 23:16 subordinate bus number rw records the highest bus number of the pci segment that resides behind PI7C21P100. reset to 00h 8.1.17 secondary latency timer register ? offset 18h bit function type description 31:24 secondary latency timer rw specifies the value of the secondary latency timer in pci bus clock units. reset to 00h in conventional pci mode reset to 40h in pci-x mode
PI7C21P100 2-port pci-x bridge advance information page 46 of 77 june 10, 2005 revision 1.06 8.1.18 i/o base address register ? offset 1ch bit function type description 7:4 i/o base address rw specifies the base of the i/o address range bits [15:12] and is used with the i/o limit register and i/ o base upper 16 bits and i/o limit upper 16-bit registers 3:2 reserved ro reserved. returns 00b when read. 1:0 32-bit i/o addressing ro returns 01b when read to indicate PI7C21P100 supports 32-bit i/o addressing 8.1.19 i/o limit register ? offset 1ch bit function type description 15:12 i/o limit address rw address bits[15:12] of the limit address for the address range of i/o operations that are passed from primary to secondary 11:10 reserved ro reserved. returns 00b when read. 9:8 32-bit i/o addressing ro returns 01b when read to indicate PI7C21P100 supports 32-bit i/o addressing 8.1.20 secondary status register ? offset 1ch bit function type description 31 detected parity error rwc detected parity error status 0: address or data parity error not detected by PI7C21P100 on the secondary 1: address or data parity erro r detected by PI7C21P100 on the secondary reset to 0 30 signaled system error rwc signaled system error status 0: PI7C21P100 did not assert serr# on the secondary 1: PI7C21P100 asserted serr# on the secondary reset to 0 29 received master abort rwc received master abort status 0: transaction not terminated with a bus master abort on the secondary 1: transaction terminated with a bus master abort on the secondary reset to 0 28 received target abort rwc received target abort status 0: transaction not terminated with a target abort 1: transaction terminated with a target abort reset to 0 27 signaled target abort rwc signaled target abort status 0: target device did not terminate tr ansaction with a target abort 1: target device terminated transaction with a target abort reset to 0 26:25 devsel# timing ro devesel# timing status 01: medium decoding. returns 01h when read. 24 data parity error rwc data parity error status 0: no data parity error detected on the secondary 1: data parity error detected on the secondary reset to 0 23 fast back-to-back enable ro fast back-to-back status 0: target not capable of decoding fa st back-to-back transactions in pci-x mode 1: target capable of decoding fast back-to-back transactions in conventional pci mode returns 0 in pci-x mode and 1 in conventional pci mode 22 reserved ro reserved. returns 0 when read.
PI7C21P100 2-port pci-x bridge advance information page 47 of 77 june 10, 2005 revision 1.06 bit function type description 21 66mhz capable ro 66mhz capable status 1: capable of 66mhz operation returns 1 when read. 20:16 reserved ro reserved. returns 00000 when read. 8.1.21 memory base register ? offset 20h bit function type description 15:4 memory base rw specifies the base of the memory mapped i/o address range bit[31:20] and is used with the memory limit register to specify a range of 32-bit addresses supported for memory mapped i/o transactions. reset to 800h 3:0 reserved ro reserved . returns 0 when read 8.1.22 memory limit register ? offset 20h bit function type description 31:20 memory limit rw specifies address bits[ 31:20] of the limit address for the address range of memory mapped i/o operations. reset to 000h 19:16 reserved ro reserved . returns 0 when read 8.1.23 prefetchable memory base register ? offset 24h bit function type description 15:4 prefetchable memory base rw specifies address bits[31:20] of the base address for the address range of prefetchable memory operations. reset to 800h 3:0 64-bit addressing ro designates 64-bit a ddressing support. returns 1h when read. 8.1.24 prefetchable memory limit register ? offset 24h bit function type description 31:20 prefetchable memory limit rw specifies address bits[31:20] of the limit address for the address range of prefetchable memory operations. reset to 800h 19:16 64-bit addressing ro designates 64-bit addressing support. returns 1h when read. 8.1.25 prefetchable base upper 32-bi t register ? offset 28h bit function type description 31:0 prefetchable base upper 32-bit rw specifies address bits[63:32] of the base address for the address range of prefetchable memory operations. reset to 0000 0000h
PI7C21P100 2-port pci-x bridge advance information page 48 of 77 june 10, 2005 revision 1.06 8.1.26 prefetchable limit upper 32-bi t register ? offset 2ch bit function type description 31:0 prefetchable limit upper 32-bit rw specifies address bits[63:32] of the limit address for the address range of prefetchable memory operations. reset to 0000 0000h 8.1.27 i/o base upper 16-bit register ? offset 30h bit function type description 15:0 i/o base upper 16-bit rw specifies address bits[31:16] of the base address for the address range of i/o operations. reset to 0000h 8.1.28 i/o limit upper 16-bit register ? offset 30h bit function type description 31:16 i/o limit upper 16-bit rw specifies address bits[31:16] of the limit address for the address range of i/o operations. reset to 0000h 8.1.29 capability pointer ? offset 34h bit function type description 7:0 capability pointer ro pointe r to a capabilities list in the co nfiguration space. returns 80h when read. 8.1.30 expansion rom base address register ? offset 38h bit function type description 31:0 expansion rom base address ro expansion rom not supported. returns 00000000h when read 8.1.31 interrupt line register ? offset 3ch bit function type description 7:0 interrupt line register rw for post progr am to initialize to ffh, defining pi 7c21p100 does not implement an interrupt pin. 8.1.32 interrupt pin register ? offset 3ch bit function type description 15:8 interrupt pin register ro defines the inte rrupt pin, but PI7C21P100 does not implement any interrupt pins. read as 00h.
PI7C21P100 2-port pci-x bridge advance information page 49 of 77 june 10, 2005 revision 1.06 8.1.33 bridge control register ? offset 3ch bit function type description 31:28 reserved ro reserved . returns 0h when read. 27 discard timer p_serr# enable rw discard timer p_serr# enable 0: does not assert p_serr# on the primary interface as a result of the expiration of either the prim ary discard timer or secondary discard timer. 1: asserts p_serr# on the primary interface as a result of the expiration of either the primary di scard timer or secondary discard timer. this bit is ignored in pci-x mode. reset to 0h. 26 master timeout status rwc master timeout status 0: no discard timer error 1: discard timer error (from primary or secondary discard timer) this bit remains 0 when in pci-x mode. reset to 0h. 25 secondary master timeout status rw secondary master timeout status 0: the secondary discard timer counts 2 15 pci clock cycles. 1: the secondary discard timer counts 2 10 pci clock cycles. if the secondary interface is in pc i-x mode, this bit is ignored. reset to 0h. 24 primary master timeout status rw primary master timeout status 0: the primary discard timer counts 2 15 pci clock cycles. 1: the primary discard timer counts 2 10 pci clock cycles. if the primary interface is in pci-x mode, this bit is ignored. reset to 0h. 23 fast back-to-back ro fast back-to-back transaction enable designates PI7C21P100 does not generate fast back-to-back transactions. returns 0 when read. 22 secondary interface reset rw secondary interface reset 0: does not force the assertion of s_rst# on the secondary interface 1: forces the assertion of s_rst# on the secondary interface. reset to 0h. 21 master abort mode rw master abort mode 0: do not report master aborts. returns ffffffffh on reads and discard data on writes. 1: report master aborts by signaling target abort if possible or by asserting serr# (if enabled). if in pci-x mode, PI7C21P100 will return a split completion message, leaving the host bridge to return ffffffffh on any non- posted transaction when the non-posted transaction ends in a master abort. reset to 0h. 20 reserved ro reserved. returns 0 when read. 19 vga enable rw vga enable 0: does not forward vga compatible memory and i/o addresses from the primary to secondary interface unless they are enabled for forwarding by the defined i/o and memory address ranges. 1: forwards vga compatible memory and i/o addresses from the primary to secondary interface (if th e i/o enable and memory enable bits are set) independent of th e defined i/o and memory address ranges and independent of the isa enable bit. 18 isa enable rw isa enable 0: forward downstream all i/o addre sses in the address defined by the i/o base and limit registers. 1: forward upstream all i/o addresse s in the address range defined by the i/o base and limit registers that are in the first 64kb of pci i/o address space reset to 0h. 17 s_serr# enable rw s_serr# enable 0: disable the forwarding of s_serr# to p_serr# 1: enable the forwarding of s_serr# to p_serr#. reset to 0h.
PI7C21P100 2-port pci-x bridge advance information page 50 of 77 june 10, 2005 revision 1.06 bit function type description 16 parity error response enable rw parity error response enable 0: ignore address and data parity e rrors on the secondary interface. 1: enable parity error detecti on on the secondary interface. 8.1.34 primary data buffering contro l register ? offset 40h bit function type description 15 reserved ro reserved . returns 0h when read. 14:12 maximum memory read byte count rw maximum memory read byte count 000: 512 bytes (default) 001: 128 bytes 010: 256 bytes 011: 512 bytes 100: 1024 bytes 101: 2048 bytes 110: 4096 bytes 111: 512 bytes maximum byte count is used by PI7C21P100 when generating read requests on the secondary interface in response to a memory read operation initiated on the primary interface which is in pci mode and bits[9:8], bits[7:6], or bits [5:4] are set to full prefetch. reset to 000 11 enable relaxed ordering rw relaxed ordering enable 0: relaxed ordering is disabled in conventional pci mode. 1: at the primary interface, read comp letions that occur after the first read completion are allowed to by pass posted writes and complete with a higher priority in conventional pci mode. in pci-x mode, the relaxed ordering bit in the attribute field will take precedence. reset to 0 10 primary special delayed read mode enable rw primary special delayed read mode enable 0: retry any primary master which repeats its transaction with command code changes. 1: allows any primary master to change memory command code (mr, mrl, mrm) after it has re ceived a retry. PI7C21P100 will complete the memory read transac tion and return data back to the primary bus master if the address and byte enables are the same. this bit is ignored in pci-x mode. reset to 0 9:8 primary read prefetch mode rw primary read prefetch mode 00: one cache line prefetch if memo ry read address is in the prefetchable range at the primary interface 01: reserved 10: full prefetch if memory read address is in the prefetchable range at the primary interface. 11: disconnect on the first dword. these bits are ignored in pci-x mode. reset to 00 7:6 primary read line prefetch mode rw primary read line prefetch mode 00: one cache line prefetch if memo ry read line address is in prefetchable range at the primary interace 01: reserved 10: full prefetch if memory read mult iple address is in prefetchable range at the primary interface 11: reserved. these bits are ignored if the pr imary interface is in pci-x mode. 5:4 primary read multiple prefetch mode rw primary read multiple prefetch mode 00: one cache line prefetch if memory read multiple address is in prefetchable range at the primary interface. 01: reserved. 10: full prefetch if memory read mult iple address is in prefetchable range at the primary interface. 11: reserved. these bits are ignored if the pr imary interface is in pci-x mode. reset to 10. 3:0 reserved ro reserved. returns 0000 when read.
PI7C21P100 2-port pci-x bridge advance information page 51 of 77 june 10, 2005 revision 1.06 8.1.35 secondary data buffering control register ? offset 40h bit function type description 31 reserved ro reserved . returns 0h when read. 30.28 maximum memory read byte count rw maximum memory read byte count 000: 512 bytes (default) 001: 128 bytes 010: 256 bytes 011: 512 bytes 100: 1024 bytes 101: 2048 bytes 110: 4096 bytes 111: 512 bytes maximum byte count is used by PI7C21P100 when generating read requests on the primary interface in response to a memory read operation initiated on the secondary interface which is in conventional pci mode and bits[9:8], bits[7:6], or bits[5:4] are set to full prefetch. reset to 000 27 enable relaxed ordering rw relaxed ordering enable 0: relaxed ordering is disabled in conventional pci mode. 1: at the secondary interface, read completions that occur after the first read completion are allowed to bypass posted writes and complete with a higher priority in conventional pci mode. in pci-x mode, the relaxed ordering bit in the attribute field will take precedence. reset to 0 26 secondary special delayed read mode enable rw secondary special delayed read mode enable 0: retry any secondary master whic h repeats its transaction with command code changes. 1: allows any secondary master to change memory command code (mr, mrl, mrm) after it has re ceived a retry. PI7C21P100 will complete the memory read transac tion and return data back to the primary bus master if the address and byte enables are the same. this bit is ignored in pci-x mode. reset to 0 25:24 secondary read prefetch mode rw secondary read prefetch mode 00: one cache line prefetch if memo ry read address is in the prefetchable range at the secondary interface 01: reserved 10: full prefetch if memory read address is in the prefetchable range at the secondary interface. 11: disconnect on the first dword. these bits are ignored in pci-x mode. reset to 00 23:22 secondary read line prefetch mode rw secondary read line prefetch mode 00: one cache line prefetch if memo ry read line address is in prefetchable range at the secondary interface 01: reserved 10: full prefetch if memory read mult iple address is in prefetchable range at the secondary interface 11: reserved. these bits are ignored if the secondary interface is in pci-x mode. 21:20 secondary read multiple prefetch mode rw secondary read multiple prefetch mode 00: one cache line prefetch if memory read multiple address is in prefetchable range at the secondary interface. 01: reserved. 10: full prefetch if memory read mult iple address is in prefetchable range at the secondary interface. 11: reserved. these bits are ignored if the secondary interface is in pci-x mode. reset to 10. 19:16 reserved ro reserved. returns 0000 when read.
PI7C21P100 2-port pci-x bridge advance information page 52 of 77 june 10, 2005 revision 1.06 8.1.36 miscellaneous control register ? offset 44h bit function type description 7:3 reserved ro reserved . returns 00000 when read. 2 primary configuration busy rw primary configuration busy 0: type 0 configuration commands accepted normally on the primary interface. 1: type 0 configuration commands re tried on the primary interface. this bit can be read from both th e primary and secondary buses, but written only from the secondary bus. reset value is based on p_cfg_busy. if p_cfg_busy is tied high, reset to 1. 1 data parity error recovery enable rw data parity error recovery enable 0: all PI7C21P100 to pass parity errors through. 1: cause serr# to be asserted when ever either master-data-parity- error bit[8] is set. reset to 1. 0 parity error behavior rw parity error behavior 0: PI7C21P100 will pass the corrupted data sequence and perr# will be asserted (if enabled), but PI7C21P100 will not complete the data and cbe# for performing completion on the initiating bus when detecting a data parity error on a non-posted write transaction. 1: transaction will be completed on the originating bus, perr# will be asserted (if enabled), he appropriate status bits will be set, the data will be discarded and no request will be queued. reset to 1. 8.1.37 extended chip control register 1 ? offset 48h bit function type description 7 reserved ro reserved . returns 0 when read. 6 bridge disconnect discard timer rw bridge disconnect discard control 0: PI7C21P100 will discard remaining data after it disconnects the external master during burst memory reads transaction on the pci source bus. 1: PI7C21P100 will keep remaining data after it disconnects the external master during burst memory reads on the pci source bus, until the external mast er returns or the discard timer expires. reset to 0. 5 memory write transaction entry control rw memory write transaction entry control 0: PI7C21P100 can accept 4 memory write transactions 1: PI7C21P100 can accept 8 memory write transactions reset to 0. 4 synchronous mode enable rw synchronous mode enable 0: synchronous mode is disabled, a nd the asynchronous clock input is supported. 1: synchronous mode is enabled and is used to decrease the frequency to frequency latenc y when PI7C21P100 is forwarding transactions through the bridge . the clock inputs have to be synchronized and the primary clock n eed to lead the secondary clock with the following combinations: primary secondary time 33mhz 33mhz 0 ? 14ns 66mhz 66mhz 0 ? 7ns 66mhz 33mhz 3 ? 14ns 133mhz 133mhz 0 ? 3ns 133mhz 66mhz 3 ? 7ns reset to 0 3 upstream memory read prefetching dynamic control rw upstream memory read prefetching dynamic control 0: enable upstream memory read prefetching dynamic control 1: disable upstream memory read prefetching dynamic control reset to 0 (described in section 4.3.6)
PI7C21P100 2-port pci-x bridge advance information page 53 of 77 june 10, 2005 revision 1.06 bit function type description 2 downstream memory read prefetching dynamic control rw downstream memory read prefetching dynamic control 0: enable downstream memory read prefetching dynamic control 1: disable downstream memory read prefetching dynamic control reset to 0 (described in section 4.3.6) 1:0 reserved ro reserved. returns 00 when read. 8.1.38 extended chip control register 2 ? offset 48h bit function type description 11:10 minimum free space in memory data fifo control (secondary) rw minimum free space in memory data fifo control (secondary) selects the minimum free space in the memory data fifo to accept memory writes on the secondary bus in pci-x mode 00: 128 bytes of free space to accept memory writes 01: 256 bytes of free space to accept memory writes 10: 512 bytes of free space to accept memory writes 11: 128 bytes of free space to accept memory writes reset to 00 9:8 minimum free space in memory data fifo control (primary) rw minimum free space in memory data fifo control (primary) selects the minimum free space in the memory data fifo to accept memory writes on the primary bus in pci-x mode 00: 128 bytes of free space to accept memory writes 01: 256 bytes of free space to accept memory writes 10: 512 bytes of free space to accept memory writes 11: 128 bytes of free space to accept memory writes reset to 00 8.1.39 arbiter mode regi ster ? offset 50h bit function type description 15:8 arbiter fairness counter rw arbiter fairness counter these bits are the initialization value of a counter used by the internal arbiter. it controls the number of pci bus cycles that the arbiter holds a device?s pci bus grant active after detecting a pci bus request from another device. the counter is re loaded whenever a new pci bus grant is asserted. for every new pci bus grant, the counter is armed to decrement when it detects the de-assertion of frame#. if the arbiter fairness counter is set to 00h, the arbiter will not remove a device?s pci bus grant until the device has de-asserted its pci bus request. reset to 08h 7 gnt# output toggling enable rw gnt# output toggling enable 0: gnt# not de-asserted after granted master asserts frame# 1: gnt# de-asserts for 1 clock after 2 clocks from the granted master asserting frame#. reset to 0 6 broken master refresh rw broken master refresh 0: a broken master will be ignored forever except when it de-asserts its req# for at least 1 clock 1: refresh broken master state afte r all other masters have been served once. reset to 0 5:2 reserved ro reserved. returns 0000 when read. 1 broken master timeout enable rw broken master timeout enable 0: broken master tim eout disabled 1: broken master timeout enabled. this enables the inte rnal arbiter to count 16 pci bus cycles while waiting for frame# to become active when a device?s pci bus gnt# is active and the pci bus is idle. if the broken master timeout expires, the pci bus gnt# for the device is de-asserted. reset to 0
PI7C21P100 2-port pci-x bridge advance information page 54 of 77 june 10, 2005 revision 1.06 bit function type description 0 external arbiter ro external arbiter 0: enable internal arbiter. 1: disable internal arbiter. reset to 0 or 1 according to the value of s_arb# during the reset. if s_arb# is tied low, then returns 0 when read. if s_arb# is tied high, then return s 1 when read. 8.1.40 arbiter enable register ? offset 54h bit function type description 7 reserved ro reserved. returns 0 when read. 6 enable arbiter 6 rw enable arbiter 6 0: disable arbitration for master 6 1: enable arbitration for master 6 reset to 1 5 enable arbiter 5 rw enable arbiter 5 0: disable arbitration for master 5 1: enable arbitration for master 5 reset to 1 4 enable arbiter 4 rw enable arbiter 4 0: disable arbitration for master 4 1: enable arbitration for master 4 reset to 1 3 enable arbiter 3 rw enable arbiter 3 0: disable arbitration for master 3 1: enable arbitration for master 3 reset to 1 2 enable arbiter 2 rw enable arbiter 2 0: disable arbitration for master 2 1: enable arbitration for master 2 reset to 1 1 enable arbiter 1 rw enable arbiter 1 0: disable arbitration for master 1 1: enable arbitration for master 1 reset to 1 0 enable arbiter 0 rw enable arbiter 0 0: disable arbitration for internal bridge request 1: enable arbitration for internal bridge request reset to 1 8.1.41 arbiter priority register ? offset 58h bit function type description 7 reserved ro reserved. returns 0 when read. 6 arbiter priority 6 rw arbiter priority 6 0: low priority request to master 6 1: high priority request to master 6 reset to 0 5 arbiter priority 5 rw arbiter priority 5 0: low priority request to master 5 1: high priority request to master 5 reset to 0 4 arbiter priority 4 rw arbiter priority 4 0: low priority request to master 4 1: high priority request to master 4 reset to 0 3 arbiter priority 3 rw arbiter priority 3 0: low priority request to master 3 1: high priority request to master 3 reset to 0
PI7C21P100 2-port pci-x bridge advance information page 55 of 77 june 10, 2005 revision 1.06 bit function type description 2 arbiter priority 2 rw arbiter priority 2 0: low priority request to master 2 1: high priority request to master 2 reset to 0 1 arbiter priority 1 rw arbiter priority 1 0: low priority request to master 1 1: high priority request to master 1 reset to 0 0 arbiter priority 0 rw arbiter priority 0 0: low priority request to internal bridge 1: high priority request to internal bridge reset to 1 8.1.42 serr# disable regi ster ? offset 5ch bit function type description 7:5 reserved ro reserved. returns 000 when read. 4 perr# on posted writes serr# disable rw perr# on posted writes serr# disable 0: assert serr# and set bit[30] offset 04h of the status register if bit[8] offset 04h in the command register is set. discard the delayed transaction. 1: disable the assertion of serr#. reset to 0 3 primary discard timer serr# disable rw primary discard timer serr# disable 0: assert serr# and update bit[30] offset 04h of the status register if the primary discard timer expire s and bit[8] offset 04h in the command register is set and bit[27] offset 3ch in the control register is set. discard the delayed transacti on and set bit[3] offset 6ch of the retry and timer status register. 1: disable the assertion of serr# if the primary discard timer expires. discard the delayed transact ion and set bit[3] offset 6ch of the retry and timer status register. reset to 0 2 secondary discard timer serr# disable rw secondary discard timer serr# disable 0: assert serr# and update bit[30] offset 04h of the status register if the secondary discard timer expi res and bit[8] offset 04h in the command register is set and bit[27] offset 3ch in the control register is set. discard the delayed transacti on and set bit[3] offset 6ch of the retry and timer status register. 1: disable the assertion of serr# if the primary discard timer expires. discard the delayed transact ion and set bit[3] offset 6ch of the retry and timer status register. reset to 0 1 primary retry count serr# disable rw primary retry count serr# disable 0: assert serr# and update bit[30] offset 04h of the status register if the primary retry counter expires and bit[8] offset 04h in the command register is set. discard th e transaction and set bit[1] offset 6ch of the retry and timer status register. 1: disable the assertion of serr# if the primary retry counter expires. discard the transaction and set bit[1] offset 6ch of the retry and timer status register. reset to 0 0 secondary retry count serr# disable rw secondary retry count serr# disable 0: assert serr# and update bit[30] offset 04h of the status register if the secondary retry counter expires and bit[8] offset 04h in the command register is set. discard th e transaction and set bit[0] offset 6ch of the retry and timer status register. 1: disable the assertion of serr# if the primary retry counter expires. discard the transaction and set bit[0] offset 6ch of the retry and timer status register. reset to 0
PI7C21P100 2-port pci-x bridge advance information page 56 of 77 june 10, 2005 revision 1.06 8.1.43 primary retry counter register ? offset 60h bit function type description 31 2g retry count control rw 2g retry count control 1: designates 2g retrie s before expiration reset to 0 30:25 reserved ro reserved. returns 000000 when read. 24 16m retry count control rw 16m retry count control 1: designates 16m retries before expiration. reset to 0 23:17 reserved ro reserved. returns 0000000 when read. 16 64k retry count control rw 64k retry count control 1: designates 64k retries before expiration. reset to 0 15:9 reserved ro reserved. returns 0000000 when read. 8 256 retry count control rw 256 retry count control 1: designates 256 retries before expiration. reset to 0 7:0 reserved ro reserved. returns 00000000 when read. the below settings are the only allowed values. other settings are not valid and will result in smaller retry counts. when the counter expires, the bridge discards the requested transaction on the primary bus and issues serr# on the primary bus if enabled. 0000 0000: no expiration limit 8000 0000: allow 2g retries before expiration 0100 0000: allow 16m retries before expiration 0001 0000: allow 64k retries before expiration 0000 0100: allow 256 retries before expiration 8.1.44 secondary retry counter register ? offset 64h bit function type description 31 2g retry count control rw 2g retry count control 1: designates 2g retrie s before expiration reset to 0 30:25 reserved ro reserved. returns 000000 when read. 24 16m retry count control rw 16m retry count control 1: designates 16m retries before expiration. reset to 0 23:17 reserved ro reserved. returns 0000000 when read. 16 64k retry count control rw 64k retry count control 1: designates 64k retries before expiration. reset to 0 15:9 reserved ro reserved. returns 0000000 when read. 8 256 retry count control rw 256 retry count control 1: designates 256 retries before expiration. reset to 0 7:0 reserved ro reserved. returns 00000000 when read. the below settings are the only allowed values. other settings are not valid and will result in smaller retry counts. when the counter expires, the bridge discards the requested transaction on the secondary bus and issues serr# on the primary bus if enabled. 0000 0000: no expiration limit 8000 0000: allow 2g retries before expiration 0100 0000: allow 16m retries before expiration 0001 0000: allow 64k retries before expiration 0000 0100: allow 256 retries before expiration
PI7C21P100 2-port pci-x bridge advance information page 57 of 77 june 10, 2005 revision 1.06 8.1.45 discard timer control re gister ? offset 68h bit function type description 7:4 reserved ro reserved. returns 0000 when read. 3 primary discard timer short duration rw primary discard timer short duration 0: use bit[24] offset 3ch of the bridge control register to indicate how many pci clocks should be a llowed before the primary discard timer expires. 1: 64 pci clocks allowed before the discard time expires. reset to 0 2 secondary discard timer short duration rw secondary discard timer short duration 0: use bit[25] offset 3ch of the bridge control register to indicate how many pci clocks should be allowed before the secondary discard timer expires. 1: 64 pci clocks allowed before the secondary discard timer expires. reset to 0 1 primary discard timer disable rw primary discard timer disable 0: enable the primary discard timer in conjunction with bit[27] offset 3ch of the bridge control register 1: disable the primary discard time r in conjunction with bit[27] offset 3ch of the bridge control register reset to 0 0 secondary discard timer disable rw secondary discard timer disable 0: enable the secondary discard timer in conjunction with bit[27] offset 3ch of the bridge control register 1: disable the secondary discard timer in conjunction with bit[27] offset 3ch of the bridge control register reset to 0 8.1.46 retry and timer status register ? offset 6ch bit function type description 7:4 reserved ro reserved. returns 0000 when read. 3 primary discard timer status rw primary discard timer status 0: the primary discard timer has not expired since the last reset. 1: the primary discard timer has expired since the last reset. reset to 0 2 secondary discard timer status rw secondary discard timer status 0: the secondary discard timer has not expired since the last reset. 1: the secondary discard timer has expired since the last reset. reset to 0 1 primary retry counter status rw primary retry counter status 0: the primary retry counter has not expired since the last request. 1: the primary retry counter has e xpired since the last request. reset to 0. 0 secondary retry counter status rw secondary retry counter status 0: the secondary retry counter has not expired since the last request. 1: the secondary retry counter has expired since the last request. reset to 0. 8.1.47 opaque memory enable re gister ? offset 70h bit function type description 7:1 reserved ro reserved. returns 0000000 when read. 0 opaque memory enable rw opaque memory enable 0: disable the opaque memory address range if opaque_en=0. 1: enable the opaque memory address range if opaque_en=1. reset to the value of opaque_en during reset.
PI7C21P100 2-port pci-x bridge advance information page 58 of 77 june 10, 2005 revision 1.06 8.1.48 opaque memory base register ? offset 74h bit function type description 15:4 opaque memory base address rw opaque memory base address address bits[31:20] of the opa que memory base address in conjunction with the opaque memory base upper 32-bit register and opaque memory limit address. in this range, memory transactions are not accepted by PI7C21P100 on both primary and secondary interfaces. reset to 000h 3:0 address select ro address select returns 0001 when read to indicate 64-bit addressing. 8.1.49 opaque memory limit re gister ? offset 74h bit function type description 31:20 opaque memory limit address rw opaque memory limit address address bits[31:20] of the opaque memory limit address in conjunction with the opaque memory limit upper 32-bit register and opaque memory base address. in th is range, memory transactions are not accepted by PI7C21P100 on both primary and secondary interfaces. reset to fffh 19:16 address select ro address select returns 0001 when read to indicate 64-bit addressing. 8.1.50 opaque memory base upper 32- bit register ? offset 78h bit function type description 31:0 opaque memory base upper 32-bit register rw opaque memory base upper 32-bit register address bits[63:32] of the opaque me mory base address. in this range, memory transactions are not accepted by PI7C21P100 on both primary and secondary interfaces. reset to ffff ffffh 8.1.51 opaque memory limit upper 32-bit register ? offset 7ch bit function type description 31:0 opaque memory base upper 32-bit register rw opaque memory base upper 32-bit register address bits[63:32] of the opaque memory limit address. in this range, memory transactions are not accepted by PI7C21P100 on both primary and secondary interfaces. reset to ffff ffffh 8.1.52 pci-x capability id register ? offset 80h bit function type description 7:0 pci-x capability id ro pci-x capability id returns 07h when read to indicate that this register set of the capabilities list is a pci-x register set.
PI7C21P100 2-port pci-x bridge advance information page 59 of 77 june 10, 2005 revision 1.06 8.1.53 next capability pointer register ? offset 80h bit function type description 15:8 next capability pointer ro next capability pointer returns 90h when read to indicate that there are more list items in the capabilities list. 8.1.54 pci-x secondary status register ? offset 80h bit function type description 31:25 reserved ro reserved. returns 0000000 when read. 24:22 secondary clock frequency ro secondary clock frequency enables the configuration software to determine what mode and what frequency PI7C21P100 set the secondary bus to the last time the secondary rst# was asserted. value max clock frequency min clk period 000 conventional mode n/a 001 66 mhz 15ns 010 100 mhz 10ns 011 133 mhz 7.5ns 1xx reserved reserved 21 split request delayed rw split request delayed 0: the bridge has not delayed a split request 1: the bridge has delayed a split request because the bridge cannot forward a transaction to the sec ondary bus because there isn?t enough room within the limit specified in the split transaction commitment limit field in the downstream split transaction control register. reset to 0 20 split completion overrun rw split completion overrun 0: PI7C21P100 has accepted all split completions. 1: PI7C21P100 has terminated a split completion on the secondary bus with retry or disconnect at the next adb because the bridge buffers were full. reset to 0 19 unexpected split completion rw unexpected split completion 0: no unexpected split completion has been received. 1: an unexpected split completion has been received with the requested id equal to the bridge ?s secondary bus number, device number 00h, and function numbe r 0 on the bridge secondary interface. reset to 0 18 split completion discarded rw split completion discarded 0: no split completion has been discarded. 1: a split completion moving toward the secondary bus has been discarded by the bridge because the requester would not accept it. reset to 0. 17 133mhz capable ro 133mhz capable returns 1 when read to indicate PI7C21P100 is capable of 133mhz operation on the secondary interface. 16 64-bit device ro 64-bit device returns a 1 when the ad interface is 64-bits wide on the secondary bus and 64bit_dev#=1. returns a 0 when 64bit_dev#=0. 8.1.55 pci-x bridge primary status register ? offset 84h bit function type description 31:22 reserved ro reserved. returns 00000000 when read.
PI7C21P100 2-port pci-x bridge advance information page 60 of 77 june 10, 2005 revision 1.06 bit function type description 21 split request delayed rw split request delayed 0: PI7C21P100 has not delayed a split request. 1: a split request moving toward the primary bus has been delayed by PI7C21P100 because there is not enough room within the limit specified in the split transacti on commitment limit field in the upstream split transaction control register. reset to 0 20 split completion overrun rw split completion overrun 0: PI7C21P100 has accepted all split completions. 1: PI7C21P100 has terminated a split completion on the primary bus with retry or disconnect at the ne xt adb because the buffers in the bridge were full. reset to 0 19 unexpected split completion rw unexpected split completion 0: no unexpected split completion has been received. 1: an unexpected split completion has been received with the requested id equal to the bri dge?s primary bus number, device number, and function number on the bridge pirmary interface. reset to 0 18 split completion discarded rw split completion discarded 0: no split completion has been discarded. 1: a split completion moving toward the primary bus has been discarded by the bridge because the requester would not accept it. reset to 0. 17 133mhz capable ro 133mhz capable returns 1 when read to indicate PI7C21P100 is capable of 133mhz operation on the primary interface. 16 64-bit device ro 64-bit device returns a 1 when the ad interface is 64-bits wide on the primary bus and p_req64#=0 at p_rst# de-asse rtion. otherwise, ad interface is 32-bits wide. 15:8 bus number ro bus number this is an additional address from which the contents of the primary bus number register on type 1 conf iguration space header is read. the bridge uses the bus number, devi ce number, and function number fields to create the completer id when responding with a split completion to a read of an internal bridge register. these fields are also used for cases when one inte rface is in conventional pci mode and the other is in pci-x mode. reset to 11111111 7:3 device number ro device number the device number (ad[15:11]) of a type 0 configuration transaction is assigned to the bridge by the c onnection of system hardware. each time the bridge is addressed by a configuration write transaction, the bridge updates this register with the contents of ad[15:11] of the address phase of the configuration transaction, regardless of which register in the bridge is addressed by the transaction. the bridge is addressed by a configuration write transaction if all of the following are true: - the transaction uses a configuration write command - idsel is asserted during the address phase - ad[1:0] are 00 (type 0 configuration transaction) - ad[10:8] of the configuration address contain the appropriate function number reset to 11111 2:0 function number ro function number the function number (ad[10:8]) of the address of a type 0 configuration transaction to which the bridge responds. reset to 000
PI7C21P100 2-port pci-x bridge advance information page 61 of 77 june 10, 2005 revision 1.06 8.1.56 secondary bus upstream split transaction register ? offset 88h bit function type description 31:16 split transaction commitment limit rw split transaction commitment limit this field indicates the cumulative sequence size of the commitment limit in units of adq?s. software is allowed to program this field to any value greater than or equal to th e contents of the split transaction capacity field. for example, if the li mit is set to ffffh, the bridge is allowed to forward all split request s of any size regardless of the amount of buffer space available. if the limit is set to 0100h or greater, causes the bridge to forward accepted split requests of any size regardless of the amount of buf fer space available. the limit can be programmed at any time after rese t. the value of the limit is equal to the split transaction capacity field reset. reset to 0020h 15:0 split transaction capability ro split transaction capability the bridge returns 0020h to indicate that there are 32 adq?s (4k bytes) available buffer space for storing split completions for memory reads. this applies to requesters on the secondary bus addressing completers on the primary bus. reset to 0020h 8.1.57 primary bus downstream split transaction register ? offset 8ch bit function type description 31:16 split transaction commitment limit rw split transaction commitment limit this field indicates the cumulative sequence size of the commitment limit in units of adq?s. software is allowed to program this field to any value greater than or equal to th e contents of the split transaction capacity field. for example, if the li mit is set to ffffh, the bridge is allowed to forward all split request s of any size regardless of the amount of buffer space available. if the limit is set to 0100h or greater, the bridge will forward accepted split requests of any size regardless of the amount of buffer space available. the limit can be programmed at any time after reset. the value of the limit is equal to the split transaction capacity field reset. reset to 0020h 15:0 split transaction capability ro split transaction capability the bridge returns 0020h to indicate that there are 32 adq?s (4k bytes) available buffer space for storing split completions for memory reads. this applies to requesters on the secondary bus addressing completers on the primary bus. reset to 0020h 8.1.58 power management id re gister ? offset 90h bit function type description 7:0 power management id ro power management id returns 01h when read indicating that this register set of the capabilities list is a power management register set.
PI7C21P100 2-port pci-x bridge advance information page 62 of 77 june 10, 2005 revision 1.06 8.1.59 next capabilities pointer register ? offset 90h bit function type description 15:8 next capabilities pointer ro next capabilities pointer returns 00h when read indicating that there are no more list items in the capabilities list. 8.1.60 power management capabilities register ? offset 90h bit function type description 31:27 pme# pin support ro pme# pin support returns 00000 when read designating that PI7C21P100 does not support the pme# pin. 26 d2 power state support ro d2 power state support returns 0 when read indicating the d2 power management state is not supported. 25 d1 power state support ro d1 power state support returns 0 when read indicating the d1 power management state is not supported. 24:22 aux current ro aux current returns 000 when read indicating pme# generation is not supported in the d3 cold power management state. 21 device specific initialization ro device specific initialization returns 0 when read indicating that no special initialization of this function beyond the standard pci c onfiguration header is required following transition to th e d0 un-initialized state. 20 reserved ro reserved. returns 0 when read. 19 pme clock ro pme clock returns 0 when read indicating pm e# generation is not supported. 18:16 version ro version returns 010 when read indicating PI7C21P100 complies with revision 2.0 of the pci power management interface specification. 8.1.61 power management control and status register ? offset 94h bit function type description 15 pme status ro pme status returns 0 when read indicating PI7C21P100 does not support the pme# pin. 14:13 data scale ro data scale returns 00 when read indicating the da ta register is not implemented. 12:9 data select ro data select returns 0000 when read indicating the data register is not implemented. 8 pme enable ro pme enable returns 0 when read indication pm e# generation is not supported. 7:2 reserved ro reserved. returns 000000 when read.
PI7C21P100 2-port pci-x bridge advance information page 63 of 77 june 10, 2005 revision 1.06 bit function type description 1:0 power state rw power state determines and reflects the current power state. if an un- implemented power state is written to this register, the bridge completes the write transaction, i gnores the write data, and does not change the value of this field. writing a value of d0 when the previous state was d3 will cause a device reset to occur without activating the secondary s_rst#. 00 d0 01 d1 (not supported) 10 d2 (not supported) 11 d3 reset to 00 8.1.62 pci-to-pci bridge support extension register ? offset 94h bit function type description 31:24 data register ro data register returns 0 when read indicating the da ta register is not implemented. 23 bus power / clock control ro bus power / clock control returns 0 when read indicating the bus power / clock control is disabled and the secondary clock cannot be controlled by PI7C21P100. 22 b2/b3 support for d3 hot ro b2/b3 support for d3 hot returns 0 when read indicating b2/b3 support for d3 hot power management state is disabled. 21:16 reserved ro reserved. returns 000000 when read. 8.1.63 secondary bus private device mask register ? offset b0h bit function type description 31:30 reserved rw reserved. returns 00 when read. 29 private device mask 13 rw private device mast 13 0: rerouting disabled for device 13 1: block assertion of s_ad[29] for configuration transactions to device 13 and assert s_ad[31] instead. 28:26 reserved rw reserved. returns 000 when read. 25 private device mask 9 rw private device mask 9 0: rerouting disabled for device 9 1: block assertion of s_ad[25] for configuration transactions to device 9 and assert s_ad[31] instead. 24 reserved rw reserved. returns 0 when read. 23 private device mask 7 rw private device mask 7 0: rerouting disabled for device 7 1: block assertion of s_ad[23] for configuration transactions to device 7 and assert s_ad[31] instead. 22 private device mask 6 rw private device mask 6 0: rerouting disabled for device 6 1: block assertion of s_ad[22] for configuration transactions to device 6 and assert s_ad[31] instead. 21 private device mask 5 rw private device mask 5 0: rerouting disabled for device 5 1: block assertion of s_ad[21] for configuration transactions to device 5 and assert s_ad[31] instead.
PI7C21P100 2-port pci-x bridge advance information page 64 of 77 june 10, 2005 revision 1.06 bit function type description 20 private device mask 4 rw private device mask 4 0: rerouting disabled for device 4 1: block assertion of s_ad[20] for configuration transactions to device 4 and assert s_ad[31] instead. 19:18 reserved rw reserved. returns 00 when read. 17 private device mask 1 rw private device mask 1 0: rerouting disabled for device 1 1: block assertion of s_ad[17] for configuration transactions to device 1 and assert s_ad[31] instead. 16:0 reserved rw reserved. returns 000000000000000000 when read. 8.1.64 miscellaneous control register 2 ? offset b8h bit function type description 15 short term caching rw short term caching 0: short term caching is disabled 1: short term caching is enabled. 14:10 reserved ro reserved. returns 00000 when read. 9 primary prefetching persistence control rw primary prefetching persistence control 0: PI7C21P100 discontinue prefetching on the secondary bus when the target disconnects, regardless of how much data has been buffered 1: PI7C21P100 continues prefetching on the secondary bus despite target disconnects until either the byte count specified by primary data buffering control register has been prefetched, or the initiator disconnects. 8 secondary prefetching persistence control rw secondary prefetching persistence control 0: PI7C21P100 discontinue prefetching on the primary bus when the target disconnects, regardless of how much data has been buffered 1: PI7C21P100 continues prefetching on the primary bus despite target disconnects until either the byte count specified by primary data buffering control register has been prefetched, or the initiator disconnects. 7:0 reserved ro reserved. returns 00h when read.
PI7C21P100 2-port pci-x bridge advance information page 65 of 77 june 10, 2005 revision 1.06 9 ieee 1149.1 compatible jtag controller an ieee 1149.1 compatible test access port (t ap) controller and associated tap pins are provided to support boundary scan in pi721p100 for board-level continuity test and diagnostics. the tap pins assigned are tck, tdi, tdo, tms and trst#. all digital input, output, input/output pins are tested except tap pins. the ieee 1149.1 test logic consists of a tap controller, an instruction register, and a group of test data registers including bypass and boundary scan registers. the tap controller is a synchronous 16-state machine dr iven by the test clock (tck) and the test mode select (tms) pins. an independent power on reset circuit is provided to ensure the machine is in test_logic_reset state at po wer-up. the jtag signal lines are not active when the pci resource is operating pci bus cycles. 9.1 instruction register PI7C21P100 implements a 4-bit instruction register to control the operation of the jtag logic. the defined instruction codes are shown in . those bit combinations that are not listed are equivalent to the bypass (1111) instruction: instruction operation code (binary) register selected operation extest 0000 boundary scan drives / receives off-chip test data sample 0100 boundary scan samples inputs / pre-loads outputs highz 0101 bypass tri-states outputs idcode 0110 device id accesses the device id register, to read manufacturer id, part number, and version number bypass 1111 bypass selected bypass register int_scan 0010 internal scan scan test 9.2 bypass register the required bypass register, a on e-bit shift register, provides the shortest path between tdi and tdo when a bypass instruction is in effect. this allows rapid movement of test data to and from other components on the board. this path can be selected when no test operation is being performed on the PI7C21P100. 9.3 device id register this register identifies pericom as the manufact urer of the device and details the part number and revision number for the device. bit type value description 31:28 ro 0h version number 27:12 ro 01a7h last 4 digits (hex) of the die part number 11:0 ro 47fh pericom identifier assigned by jedec bit 0 is set to 1
PI7C21P100 2-port pci-x bridge advance information page 66 of 77 june 10, 2005 revision 1.06 9.4 boundary scan register the boundary scan register is a required set of serial-shiftab le register cells, formed by connecting boundary scan cells placed at the device?s signal pins into a shift register path. the vdd, vss, and jtag pins are not in the bo undary-scan chain. the input to the shift register is tdi and the output from the shift re gister is tdo. there are 4 different types of boundary scan cells, based on the function of each signal pin. the boundary scan register cells are dedicated logic and do not have any system function. data may be loaded into the boundary-scan regi ster master cells from the device input pins and output pin-drivers in parallel by the mandatory sample and extest instructions. parallel loading takes place on the rising edge of tck. 9.5 jtag boundary register order table 9-1 jtag boundary scan register boundary scan register number pin name ball location type tri-state control cell 0 p_ack64# a2 bidir 208 1 p_ad[0] b13 bidir 209 2 p_ad[1] c13 bidir 210 3 p_ad[2] b14 bidir 211 4 p_ad[3] c15 bidir 212 5 p_ad[4] a19 bidir 213 6 p_ad[5] b16 bidir 214 7 p_ad[6] c16 bidir 215 8 p_ad[7] a20 bidir 216 9 p_ad[8] b17 bidir 217 10 p_ad[9] c17 bidir 218 11 p_ad[10] c19 bidir 219 12 p_ad[11] d18 bidir 220 13 p_ad[12] f22 bidir 221 14 p_ad[13] f20 bidir 222 15 p_ad[14] g22 bidir 223 16 p_ad[15] b20 bidir 224 17 p_ad[16] g21 bidir 225 18 p_ad[17] h22 bidir 226 19 p_ad[18] h21 bidir 227 20 p_ad[19] j22 bidir 228 21 p_ad[20] j21 bidir 229 22 p_ad[21] k22 bidir 230 23 p_ad[22] d23 bidir 231 24 p_ad[23] k21 bidir 232 25 p_ad[24] e23 bidir 233 26 p_ad[25] k20 bidir 234 27 p_ad[26] g23 bidir 235 28 p_ad[27] l22 bidir 236 29 p_ad[28] l21 bidir 237 30 p_ad[29] m22 bidir 238 31 p_ad[30] m21 bidir 239 32 p_ad[31] j23 bidir 240
PI7C21P100 2-port pci-x bridge advance information page 67 of 77 june 10, 2005 revision 1.06 boundary scan register number pin name ball location type tri-state control cell 33 p_ad[32] l1 bidir 241 34 p_ad[33] j1 bidir 242 35 p_ad[34] j2 bidir 243 36 p_ad[35] h1 bidir 244 37 p_ad[36] g1 bidir 245 38 p_ad[37] j3 bidir 246 39 p_ad[38] e1 bidir 247 40 p_ad[39] h2 bidir 248 41 p_ad[40] h3 bidir 249 42 p_ad[41] g3 bidir 250 43 p_ad[42] f2 bidir 251 44 p_ad[43] b1 bidir 252 45 p_ad[44] f3 bidir 253 46 p_ad[45] e3 bidir 254 47 p_ad[46] f4 bidir 255 48 p_ad[47] d2 bidir 256 49 p_ad[48] c2 bidir 257 50 p_ad[49] b5 bidir 258 51 p_ad[50] b6 bidir 259 52 p_ad[51] d6 bidir 260 53 p_ad[52] b7 bidir 261 54 p_ad[53] c7 bidir 262 55 p_ad[54] b3 bidir 263 56 p_ad[55] b8 bidir 264 57 p_ad[56] a3 bidir 265 58 p_ad[57] b9 bidir 266 59 p_ad[58] c9 bidir 267 60 p_ad[59] b10 bidir 268 61 p_ad[60] a4 bidir 269 62 p_ad[61] c10 bidir 270 63 p_ad[62] d10 bidir 271 64 p_ad[63] b11 bidir 272 65 p_cbe[0] a13 bidir 273 66 p_cbe[1] b18 bidir 274 67 p_cbe[2] d14 bidir 275 68 p_cbe[3] a15 bidir 276 69 p_cbe[4] a5 bidir 277 70 p_cbe[5] c11 bidir 278 71 p_cbe[6] b12 bidir 279 72 p_cbe[7] a7 bidir 280 73 p_clk e21 input - 74 p_devsel d21 bidir 281 75 p_frame a17 bidir 282 76 p_gnt c20 input - 77 p_idsel b19 input - 78 p_irdy a16 bidir 283 79 p_lock c14 input - 80 p_drvr e2 input - 81 p_par c18 bidir 284 82 p_par64 a9 bidir 285 83 p_cfg_busy c6 input - 84 p_perr c8 bidir 286
PI7C21P100 2-port pci-x bridge advance information page 68 of 77 june 10, 2005 revision 1.06 boundary scan register number pin name ball location type tri-state control cell 85 p_req64 c12 bidir 287 86 p_req b21 output 288 87 p_rst r3 input - 88 p_serr b4 output 289 89 p_stop c4 bidir 290 90 p_trdy b15 bidir 291 91 s_ack64 aa8 bidir 292 92 s_ad[0] aa9 bidir 293 93 s_ad[1] ab9 bidir 294 94 s_ad[2] ac9 bidir 295 95 s_ad[3] ac11 bidir 296 96 s_ad[4] ab11 bidir 297 97 s_ad[5] ac15 bidir 298 98 s_ad[6] aa12 bidir 299 99 s_ad[7] aa13 bidir 300 100 s_ad[8] ac17 bidir 301 101 s_ad[9] ab15 bidir 302 102 s_ad[10] aa16 bidir 303 103 s_ad[11] y18 bidir 304 104 s_ad[12] ab18 bidir 305 105 s_ad[13] aa20 bidir 306 106 s_ad[14] v20 bidir 307 107 s_ad[15] w21 bidir 308 108 s_ad[16] v21 bidir 309 109 s_ad[17] v22 bidir 310 110 s_ad[18] u21 bidir 311 111 s_ad[19] u22 bidir 312 112 s_ad[20] t22 bidir 313 113 s_ad[21] w23 bidir 314 114 s_ad[22] r21 bidir 315 115 s_ad[23] t23 bidir 316 116 s_ad[24] r22 bidir 317 117 s_ad[25] n23 bidir 318 118 s_ad[26] p20 bidir 319 119 s_ad[27] m23 bidir 320 120 s_ad[28] p21 bidir 321 121 s_ad[29] p22 bidir 322 122 s_ad[30] n21 bidir 323 123 s_ad[31] n22 bidir 324 124 s_ad[32] k4 bidir 325 125 s_ad[33] k3 bidir 326 126 s_ad[34] k2 bidir 327 127 s_ad[35] l3 bidir 328 128 s_ad[36] l2 bidir 329 129 s_ad[37] r1 bidir 330 130 s_ad[38] m3 bidir 331 131 s_ad[39] m2 bidir 332 132 s_ad[40] n3 bidir 333 133 s_ad[41] n2 bidir 334 134 s_ad[42] u1 bidir 335 135 s_ad[43] p4 bidir 336 136 s_ad[44] w1 bidir 337
PI7C21P100 2-port pci-x bridge advance information page 69 of 77 june 10, 2005 revision 1.06 boundary scan register number pin name ball location type tri-state control cell 137 s_ad[45] p3 bidir 338 138 s_ad[46] y1 bidir 339 139 s_ad[47] p2 bidir 340 140 s_ad[48] r3 bidir 341 141 s_ad[49] r2 bidir 342 142 s_ad[50] t3 bidir 343 143 s_ad[51] t2 bidir 344 144 s_ad[52] u3 bidir 345 145 s_ad[53] u2 bidir 346 146 s_ad[54] v4 bidir 347 147 s_ad[55] v2 bidir 348 148 s_ad[56] y3 bidir 349 149 s_ad[57] y6 bidir 350 150 s_ad[58] aa5 bidir 351 151 s_ad[59] aa6 bidir 352 152 s_ad[60] ab6 bidir 353 153 s_ad[61] aa7 bidir 354 154 s_ad[62] ab7 bidir 355 155 s_ad[63] ab8 bidir 356 156 s_cbe[0] ab12 bidir 357 157 s_cbe[1] ab16 bidir 358 158 s_cbe[2] ab14 bidir 359 159 s_cbe[3] aa15 bidir 360 160 s_cbe[4] ac8 bidir 361 161 s_cbe[5] aa11 bidir 362 162 s_cbe[6] ab10 bidir 363 163 s_cbe[7] y10 bidir 364 164 s_clk ab23 input - 165 s_clk_stable w3 input - 166 s_devsel ac21 bidir 365 167 s_frame aa14 bidir 366 168 s_gnt[1] aa19 output 202 169 s_gnt[2] ab1 output 203 170 s_gnt[3] y2 output 204 171 s_gnt[4] ac5 output 205 172 s_gnt[5] ab4 output 206 173 s_gnt[6] ac4 output 207 174 s_arb t21 input - 175 s_irdy ac19 bidir 367 176 s_lock ac20 bidir 368 177 s_drvr ac7 input - 178 s_par aa17 bidir 369 179 s_par64 aa10 bidir 370 180 s_pcixcap r23 input - 181 s_pcixcap_pu aa1 output 376 182 s_perr ab17 bidir 371 183 s_req[1] aa23 input - 184 s_req[2] aa2 input - 185 s_req[3] w2 input - 186 s_req[4] ab3 input - 187 s_req[5] ab5 input - 188 s_req64 ab13 input 372
PI7C21P100 2-port pci-x bridge advance information page 70 of 77 june 10, 2005 revision 1.06 boundary scan register number pin name ball location type tri-state control cell 189 s_req[6] ac3 input - 190 s_rst u23 output - 191 s_sel100 v3 input - 192 s_serr ab19 input - 193 s_stop ab20 bidir 373 194 s_trdy y14 bidir 374 195 bar_en g2 input - 196 reserved d1 input - 197 xclk_out d3 output 375 198 s_idsel aa22 input - 199 64bit_dev y22 input - 200 idsel_route ac22 - - 201 opaque_en aa18 input - 202 - - control - 203 - - control - 204 - - control - 205 - - control - 206 - - control - 207 - - control - 208 - - control - 209 - - control - 210 - - control - 211 - - control - 212 - - control - 213 - - control - 214 - - control - 215 - - control - 216 - - control - 217 - - control - 218 - - control - 219 - - control - 220 - - control - 221 - - control - 222 - - control - 223 - - control - 224 - - control - 225 - - control - 226 - - control - 227 - - control - 228 - - control - 229 - - control - 230 - - control - 231 - - control - 232 - - control - 233 - - control - 234 - - control - 235 - - control - 236 - - control - 237 - - control - 238 - - control - 239 - - control - 240 - - control -
PI7C21P100 2-port pci-x bridge advance information page 71 of 77 june 10, 2005 revision 1.06 boundary scan register number pin name ball location type tri-state control cell 241 - - control - 242 - - control - 243 - - control - 244 - - control - 245 - - control - 246 - - control - 247 - - control - 248 - - control - 249 - - control - 250 - - control - 251 - - control - 252 - - control - 253 - - control - 254 - - control - 255 - - control - 256 - - control - 257 - - control - 258 - - control - 259 - - control - 260 - - control - 261 - - control - 262 - - control - 263 - - control - 264 - - control - 265 - - control - 266 - - control - 267 - - control - 268 - - control - 269 - - control - 270 - - control - 271 - - control - 272 - - control - 273 - - control - 274 - - control - 275 - - control - 276 - - control - 277 - - control - 278 - - control - 279 - - control - 280 - - control - 281 - - control - 282 - - control - 283 - - control - 284 - - control - 285 - - control - 286 - - control - 287 - - control - 288 - - control - 289 - - control - 290 - - control - 291 - - control - 292 - - control -
PI7C21P100 2-port pci-x bridge advance information page 72 of 77 june 10, 2005 revision 1.06 boundary scan register number pin name ball location type tri-state control cell 293 - - control - 294 - - control - 295 - - control - 296 - - control - 297 - - control - 298 - - control - 299 - - control - 300 - - control - 301 - - control - 302 - - control - 303 - - control - 304 - - control - 305 - - control - 306 - - control - 307 - - control - 308 - - control - 309 - - control - 310 - - control - 311 - - control - 312 - - control - 313 - - control - 314 - - control - 315 - - control - 316 - - control - 317 - - control - 318 - - control - 319 - - control - 320 - - control - 321 - - control - 322 - - control - 323 - - control - 324 - - control - 325 - - control - 326 - - control - 327 - - control - 328 - - control - 329 - - control - 330 - - control - 331 - - control - 332 - - control - 333 - - control - 334 - - control - 335 - - control - 336 - - control - 337 - - control - 338 - - control - 339 - - control - 340 - - control - 341 - - control - 342 - - control - 343 - - control - 344 - - control -
PI7C21P100 2-port pci-x bridge advance information page 73 of 77 june 10, 2005 revision 1.06 boundary scan register number pin name ball location type tri-state control cell 345 - - control - 346 - - control - 347 - - control - 348 - - control - 349 - - control - 350 - - control - 351 - - control - 352 - - control - 353 - - control - 354 - - control - 355 - - control - 356 - - control - 357 - - control - 358 - - control - 359 - - control - 360 - - control - 361 - - control - 362 - - control - 363 - - control - 364 - - control - 365 - - control - 366 - - control - 367 - - control - 368 - - control - 369 - - control - 370 - - control - 371 - - control - 372 - - control - 373 - - control - 374 - - control - 375 - - control - 376 - - control -
PI7C21P100 2-port pci-x bridge advance information page 74 of 77 june 10, 2005 revision 1.06 10 electrical information 10.1 maximum ratings stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. symbol parameter rating units v dd core logic power supply tbd v v dd2 i/o power supply voltage tbd v v in input voltage tbd v v out output voltage tbd v t a ambient operating temperature 0 to 70 c t j maximum junction temperature 125 c t stg storage temperature -55 to 125 c p wc worst case power dissipation tbd w i out short circuit output current tbd ma 10.2 dc specifications rating symbol parameter min typ max units v dd core logic power supply 2.3 2.5 2.7 v v dd2 i/o power supply voltage 3.0 3.3 3.6 v v ih input high voltage 2.0 - v ddi * + 0.5 v v il input low voltage -0.3 - 0.3 v ddi * v c in input pin capacitance - - 8.0 pf * v ddi is in reference to the power supply of the input device. 10.3 ac specifications figure 10-1 pci signal timing measurements
PI7C21P100 2-port pci-x bridge advance information page 75 of 77 june 10, 2005 revision 1.06 table 10-1 ac timing specifications pci-x mode pci-x 133 pci-x 100 pci-x 66 symbol parameter min max min max min max units t su input setup time to clk ? bussed signals 1.2 - 1.2 - 1.7 - ns t su(ptp) input setup time to clk ? point-to- point signals 1.2 - 1.2 - 1.7 - ns t h input signal hold time from clk 0.5 - 0.5 - 0.5 - ns t val clk to signal valid delay ? bussed signals 0.7 3.8 0.7 3.8 0.7 3.8 ns t val(ptp) clk to signal valid delay ? point- to-point signals 0.7 3.8 0.7 3.8 0.7 3.8 ns t on float to active delay 0 - 0 - 0 - ns t off active to float delay - 7 - 7 - 7 ns table 10-2 ac timing specifications conventional pci mode pci 66 pci 33 symbol parameter min max min max units t su input setup time to clk ? bussed signals 3 - 7 - ns t su(ptp) input setup time to clk ? point-to- point signals 5 - 10, 12 - ns t h input signal hold time from clk 0 - 0 - ns t val clk to signal valid delay ? bussed signals 2 6 2 11 ns t val(ptp) clk to signal valid delay ? point- to-point signals 2 6 2 12 ns t on float to active delay 2 - 2 - ns t off active to float delay - 14 - 14 ns 10.4 power consumption rating parameter min typ max units power dissipation for v dd (2.5v) 1.33 w power dissipation for v dd2 (3.3v) 0.46 w *running at 133mhz
PI7C21P100 2-port pci-x bridge advance information page 76 of 77 june 10, 2005 revision 1.06 11 mechanical information figure 11-1 package diagram 31 x 31mm 304-pin csbga 12 ordering information part number speed pin ? package temperature PI7C21P100nh 133mhz 304-pins ? csga 0c to 85c PI7C21P100nh 133mhz pb-free & green, 304-pins - csbga 0c to 85c
PI7C21P100 2-port pci-x bridge advance information page 77 of 77 june 10, 2005 revision 1.06 notes:

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